Variable resistance memory stack with treated sidewalls
Memory devices and methods for fabricating memory devices have been disclosed. One such method includes forming a memory stack out of a plurality of elements. A sidewall liner is formed on a sidewall of the memory stack using a physical vapor deposition (PVD) process, including an adhesion species and a dielectric, such that the adhesion species intermixes with an element of the memory stack to terminate unsatisfied atomic bonds of the element and the dielectric forms a dielectric film with the adhesive species on the sidewall.
1. A memory system comprising:
a controller to control the system; and
a memory device, coupled to the controller, the memory device comprising:
a memory stack defined in part by sidewalls, comprising:
a first carbon electrode;
a selector device over the first carbon electrode;
a second carbon electrode over the selector device;
a phase change material over the second carbon electrode; and
a third carbon electrode over the phase change material; and
a sidewall liner material on sidewalls of the memory stack wherein the sidewall liner comprises a physical vapor deposited BN x such that the boron is configured to intermix with the carbon of the electrodes at an interface of the sidewall liner material and the sidewalls.
2. The memory system of claim 1 , wherein the selector device comprises one or more of Selenium (Se), Arsenic (As), Germanium (Ge), Tin (Sn), Tellurium (Te), Silicon (Si), Lead (Pb), Carbon (C), and/or Bismuth (Bi).
3. The memory system of claim 1 , wherein the phase change material comprises one or more of Germanium (Ge), Antimony (Sb), Tellurium (Te), Indium (In), Aluminum (Al), Gallium (Ga), Tin (Sn), Bismuth (Bi), Sulphur (S), Oxygen (O), Gold (Au), Palladium (Pd), Copper (Cu), Cobalt (Co), Silver (Ag), and/or Platinum (Pt).
4. The memory system of claim 1 , further comprising a word line coupled to the first carbon electrode.
5. The memory system of claim 4 , wherein the memory device comprises multiple memory stacks.
6. The memory system of claim 5 , wherein the multiple memory stacks include memory stacks in multiple vertically arranged decks of memory stacks.
7. The memory system of claim 5 , further comprising a dielectric fill material between first and second memory stacks of the multiple memory stacks.
8. The memory system of claim 6 , wherein a first memory stack in a first deck and a second memory stack in a second vertically arranged deck are coupled to a common bit line extending between the first and second decks.
9. The memory system of claim 5 , wherein a first memory stack in a first deck and a second memory stack in a second vertically arranged deck are coupled to a common word line extending between the first and second decks.
10. The memory system of claim 1 , wherein the controller is coupled to the memory device over one or more buses communicating control, address, and data signals.
11. The memory system of claim 1 , wherein the controller is a separate integrated circuit from the memory device.
12. A memory system, comprising:
a controller to control the system; and
a memory device, coupled to the controller, the memory device comprising:
multiple memory stacks defined in part by a respective sidewalls, such memory stacks each comprising:
a first electrode;
a selector device over the first electrode;
a second electrode over the selector device;
a variable resistance material over the second electrode; and
a third electrode over the variable resistance material;
wherein at least one of the first, second, and third electrodes comprises carbon; and
a sidewall liner material on sidewalls of the multiple memory stacks wherein the sidewall liner comprises an adhesion species;
wherein the sidewall liner material is formed by a radio frequency physical vapor deposition (RF PVD) process, such that the adhesion species is configured to intermix with the carbon of the one or more electrodes at an interface of the sidewall liner material and the sidewall of the respective memory stack.
13. The memory system of claim 12 , wherein the sidewall liner material further comprises a dielectric material.
14. The memory system of claim 12 , wherein the adhesion species comprises boron.
15. The memory system of claim 14 , wherein the sidewall liner material comprises boron nitride (BN x ).
16. The memory system of claim 15 , wherein the RF PVD process is performed in a PVD chamber utilizing a boron nitride (BN x ) target.
17. The memory system of claim 16 , wherein a plasma of a gas comprising argon is formed in the PVD chamber.
18. The memory system of claim 12 , wherein each of the first, second, and third electrodes is formed of carbon.
19. The memory system of claim 12 , wherein the variable resistance material is a phase change material, and wherein the phase change material comprises one or more of Germanium (Ge), Antimony (Sb), Tellurium (Te), Indium (In), Aluminum (Al), Gallium (Ga), Tin (Sn), Bismuth (Bi), Sulphur (S), Oxygen (O), Gold (Au), Palladium (Pd), Copper (Cu), Cobalt (Co), Silver (Ag), and/or Platinum (Pt).
20. The memory system of claim 12 , wherein the selector device comprises one or more of Selenium (Se), Arsenic (As), Germanium (Ge), Tin (Sn), Tellurium (Te), Silicon (Si), Lead (Pb), Carbon (C), and/or Bismuth (Bi).