Transistors
Some embodiments include integrated circuits having first and second transistors. The first transistor is wider than the second transistor. The first and second transistors have first and second active regions, respectively. Dielectric features are associated with the first active region and break up the first active region. The second active region is not broken up to the same extent as the first active region. Some embodiments include methods of forming transistors. Active areas of first and second transistors are formed. The active area of the first transistor is wider than the active area of the second transistor. Dielectric features are formed in the active area of the first transistor. The active area of the first transistor is broken up to a different extent than the active area of the second transistor. The active areas of the first and second transistors are simultaneously doped.
1 - 22 . (canceled)
23 . A transistor comprising:
a gate comprising a first side opposite a second side;
a drain region spaced from the first side of the gate;
a source region spaced from the second side of the gate; and
at least one dielectric feature between the gate and one of the source and drain regions.
24 . The transistor of claim 23 further comprising active regions adjacent the opposites sides of the gate, the active regions comprising the same dopant concentration.
25 . The transistor of claim 23 wherein the other of the one of the source and drain regions has no dielectric features.
26 . The transistor of claim 23 wherein the at least one dielectric feature comprises two or more dielectric features.
27 . The transistor of claim 23 wherein the at least one dielectric feature comprises at least three dielectric features.
28 . The transistor of claim 23 comprising a high-voltage transistor.
29 . The transistor of claim 23 wherein the at least one dielectric feature is located between the gate and the source region.
30 . The transistor of claim 23 wherein the at least one dielectric feature is located between the gate and the drain region.
31 . The transistor of claim 23 electrically coupled to a flash memory array.
32 . The transistor of claim 23 electrically coupled to a NAND array.
33 . The transistor of claim 23 further comprising active regions adjacent the opposites sides of the gate, the active regions comprising lightly-doped diffusion regions.
34 . The transistor of claim 23 wherein the at least one dielectric feature comprises a plurality of dielectric features, the plurality of the dielectric features are spaced along the width direction of the transistor.
35 . The transistor of claim 23 wherein the at least one dielectric feature comprises at least two dielectric features spaced along the width direction of the transistor.
36 . The transistor of claim 23 wherein the at least one dielectric feature comprises at least three dielectric features spaced along the width direction of the transistor.
37 . The transistor of claim 23 wherein the one of the source and drain regions is configured to carry high-voltage in an off-state of the transistor.