Host accelerated operations in managed NAND devices

1. A device for host accelerated operations in managed NAND devices, the device comprising:

a machine readable medium including a data structure with keys; and

a controller configured to:

receive an operation, the operation including address data with a logical address portion and a physical address portion;

extract an index value from the physical address portion;

extract a location value from the physical address portion;

retrieve a key from the data structure using the index value;

invoke a reversible function using the index value and the location value to produce a physical address; and

perform the operation using the physical address.

2. The device of claim 1 , wherein the reversible function performs permutation on the key and the location value to produce the physical address.

3. The device of claim 1 , wherein the data structure is a table store, and wherein the machine readable medium is volatile memory.

4. The device of claim 3 , wherein, to retrieve the key using the index value, the controller is configured to:

extract a logical address from the logical address portion; and

combine the logical address with the index value to locate the key.

5. The device of claim 1 , wherein the operation is a write request, and wherein, to perform the operation, the controller is configured to:

write data of the write request to a second physical address;

invoke a physically unclonable function (PUF) to create a random key;

store the random key in the data structure with a second index value;

invoke the reversible function on the second physical address using the random key to produce a second location value; and

provide the second location value and the second index value to an initiator of the write request.

6. The device of claim 5 , wherein, to store the random key in the data structure, the controller is configured to generate the second index value.

7. The device of claim 5 , wherein the PUF is implemented in hardware of a controller of the NAND device.

8. A method for host accelerated operations in managed NAND devices, the method comprising:

receiving an operation at a controller of a NAND device, the operation including address data with a logical address portion and a physical address portion;

extracting an index value from the physical address portion;

extracting a location value from the physical address portion;

retrieving a key using the index value;

invoking a reversible function using the index value and the location value to produce a physical address; and

performing the operation using the physical address.

9. The method of claim 8 , wherein the reversible function performs permutation on the key and the location value to produce the physical address.

10. The method of claim 8 , wherein retrieving the key using the index value includes using the index value to locate the key in a table store in volatile memory of the NAND device.

11. The method of claim 10 , wherein retrieving the key using the index value includes:

extracting a logical address from the logical address portion; and

combining the logical address with the index value to locate the key.

12. The method of claim 8 , wherein the operation is a write request, and wherein performing the operation includes:

writing data of the write request to a second physical address;

invoking a physically unclonable function (PUF) to create a random key;

storing the random key in a data structure with a second index value;

invoking the reversible function on the second physical address using the random key to produce a second location value; and

providing the second location value and the second index value to an initiator of the write request.

13. The method of claim 12 , wherein storing the random key in the data structure includes generating the second index value.

14. The method of claim 12 , wherein the PUF is implemented in hardware of a controller of the NAND device.

15. A machine readable medium including instructions for host accelerated operations in managed NAND devices, the instructions, when executed by processing circuitry of a machine, cause the processing circuitry to perform operations comprising:

receiving an operation at a controller of a NAND device, the operation including address data with a logical address portion and a physical address portion;

extracting an index value from the physical address portion;

extracting a location value from the physical address portion;

retrieving a key using the index value;

invoking a reversible function using the index value and the location value to produce a physical address; and

performing the operation using the physical address.

16. The machine readable medium of claim 15 , wherein the reversible function performs permutation on the key and the location value to produce the physical address.

17. The machine readable medium of claim 15 , wherein retrieving the key using the index value includes using the index value to locate the key in a table store in volatile memory of the NAND device.

18. The machine readable medium of claim 17 , wherein retrieving the key using the index value includes:

extracting a logical address from the logical address portion; and

combining the logical address with the index value to locate the key.

19. The machine readable medium of claim 15 , wherein the operation is a write request, and wherein performing the operation includes:

writing data of the write request to a second physical address;

invoking a physically unclonable function (PUF) to create a random key;

storing the random key in a data structure with a second index value;

invoking the reversible function on the second physical address using the random key to produce a second location value; and

providing the second location value and the second index value to an initiator of the write request.

20. The machine readable medium of claim 19 , wherein storing the random key in the data structure includes generating the second index value.

21. The machine readable medium of claim 19 , wherein the PUF is implemented in hardware of a controller of the NAND device.