Methods of forming an array of elevationally-extending strings of memory cells comprising a programmable charge storage transistor and arrays of elevationally-extending strings of memory cells comprising a programmable charge storage transistor

1. An array of elevationally-extending strings of memory cells, the memory cells individually comprising a programmable charge storage transistor, the array comprising:

a substrate comprising a first region containing memory cells and a second region not containing memory cells laterally of the first region, the first region comprising vertically-alternating tiers of insulative material and control gate material, the second region comprising vertically-alternating tiers of different composition insulating materials laterally of the first region;

a channel pillar comprising semiconductive channel material extending elevationally through multiple of the vertically-alternating tiers within the first region;

tunnel insulator, programmable charge storage material, and control gate blocking insulator between the channel pillar and the control gate material of individual of the tiers of the control gate material within the first region;

conductive vias extending elevationally through the vertically-alternating tiers in the second region; and

an elevationally-extending wall laterally between the first and second regions, the wall comprising the programmable charge storage material and the semiconductive channel material.

2. The array of claim 1 wherein the wall is laterally spaced from a row of the channel pillars and extends along the row aside multiple of the channel pillars in the row.

3. The array of claim 2 wherein the wall extends along at least four channel pillars in the row.

4. The array of claim 2 wherein the wall is parallel with the row.

5. The array of claim 2 wherein the wall is horizontally straight-linear.

6. The array of claim 1 wherein individual tiers of the control gate material are directly against the wall on a first region-side of the wall.

7. The array of claim 6 wherein the control gate material is not directly against either of the programmable charge storage material or the semiconductive channel material of the wall.

8. The array of claim 1 wherein the wall comprises the tunnel insulator and the control gate blocking insulator.

9. The array of claim 8 wherein individual tiers of the control gate material are directly against the control gate blocking insulator of the wall on a first region-side of the wall.

10. The array of claim 1 wherein the wall comprises laterally outer linings of the programmable charge storage material and the semiconductive channel material and a central core comprising dielectric material.

11. The method of claim 10 wherein the wall comprises laterally-outermost linings of the control gate blocking insulator.

12. The array of claim 1 wherein, the wall is a first wall; and

further comprising:

a second elevationally-extending wall comprising the programmable charge storage material and the semiconductive channel material, the second wall angling relative to the first wall.

13. The array of claim 12 wherein the second wall joins with the first wall and comprises an angling extension of the first wall.

14. An array of elevationally-extending strings of memory cells, the memory cells individually comprising a programmable charge storage transistor, the array comprising:

a substrate comprising a first region containing memory cells and a second region not containing memory cells laterally of the first region, the first region comprising vertically-alternating tiers of insulative material and control gate material, the second region comprising vertically-alternating tiers of different composition insulating materials laterally of the first region;

a channel pillar comprising semiconductive channel material extending elevationally through multiple of the vertically-alternating tiers within the first region;

tunnel insulator, programmable charge storage material, and control gate blocking insulator between the channel pillar and the control gate material of individual of the tiers of the control gate material within the first region;

conductive vias extending elevationally through the vertically-alternating tiers in the second region; and

an elevationally-extending wall completely encircling an island comprising the conductive vias, the wall comprising the programmable charge storage material and the semiconductive channel material.

15. The array of claim 5 wherein the row is horizontally straight-linear, the wall being parallel with the row.

16. The array of claim 1 wherein the wall is vertical or within 10° of vertical.

17. An array of elevationally-extending strings of memory cells, the memory cells individually comprising a programmable charge storage transistor, the array comprising:

a substrate comprising a first region containing memory cells and a second region not containing memory cells laterally of the first region, the first region comprising vertically-alternating tiers of insulative material and control gate material, the second region comprising vertically-alternating tiers of different composition insulating materials laterally of the first region;

a channel pillar comprising semiconductive channel material extending elevationally through multiple of the vertically-alternating tiers within the first region;

programmable charge storage material between the channel pillar and the control gate material of individual of the tiers of the control gate material within the first region;

conductive vias extending elevationally through the vertically-alternating tiers in the second region; and

an elevationally-extending wall laterally between the first and second regions, the wall comprising the programmable charge storage material and the semiconductive channel material.

18. An array of elevationally-extending strings of memory cells, the memory cells individually comprising a programmable charge storage transistor, the array comprising:

a substrate comprising a first region containing memory cells and a second region not containing memory cells laterally of the first region, the first region comprising vertically-alternating tiers of insulative material and control gate material, the second region comprising vertically-alternating tiers of different composition insulating materials laterally of the first region;

a channel pillar comprising semiconductive channel material extending elevationally through multiple of the vertically-alternating tiers within the first region;

programmable charge storage material between the channel pillar and the control gate material of individual of the tiers of the control gate material within the first region;

conductive vias extending elevationally through the vertically-alternating tiers in the second region; and

an elevationally-extending wall completely encircling an island comprising the conductive vias, the wall comprising the programmable charge storage material and the semiconductive channel material.