Apparatus having dice to perform refresh operations

1. An apparatus comprising:

a chip stack structure comprising a first memory chip and a second memory chip stacked over the first memory chip; and

an interface chip coupled to the chip stack structure,

wherein the interface chip is configured to transfer a first input clock signal based on an original clock signal to the first memory chip, and a second input clock signal based on the original clock signal to the second memory chip, and to independently transfer a first command signal to the first memory chip and a second command signal to the second memory chip, and wherein the interface chip further comprises an oscillator configured to produce the original clock signal.

2. The apparatus of claim 1 ,

wherein the first memory chip is configured to perform a first refresh operation on a plurality of first memory cells in response to the first input clock signal and the first command signal; and

wherein the second memory chip is configured to perform a second refresh operation on a plurality of second memory cells in response to the second input clock signal and the second command signal.

3. An apparatus comprising:

a chip stack structure comprising a first memory chip and a second memory chip stacked over the first memory chip; and

an interface chip coupled to the chip stack structure,

wherein the interface chip is configured to transfer a clock signal to both of the first memory chip and the second memory chip, and to independently transfer a first command signal to the first memory chip and a second command signal to the second memory chip,

wherein the interface chip comprises a first terminal supplied with the first command signal and a second terminal supplied with the second command signal;

wherein the first memory chip comprises a third terminal coupled to the first terminal and a fourth terminal coupled to the second terminal; and

wherein the second memory chip comprises a fifth terminal coupled to the second terminal by way of the fourth terminal.

4. The apparatus of claim 1 , wherein the interface chip comprises a first terminal supplied with the first input clock signal;

wherein the first memory chip comprises a second terminal coupled to the first terminal; and

wherein the second memory chip comprises a third terminal coupled to the first terminal by way of the second terminal.

5. The apparatus of claim 1 , wherein the interface chip comprises a first terminal supplied with the first input clock signal and a second terminal supplied with the second input clock signal having a different amount of delay from the first input clock signal at the first terminal;

wherein the first memory chip comprises a third terminal coupled to the first terminal and a fourth terminal coupled to the second terminal; and

wherein the second memory chip comprises a fifth terminal coupled to the second terminal by way of the fourth terminal.

6. An apparatus comprising:

a chip stack structure comprising a first memory chip and a second memory chip stacked over the first memory chip; and

an interface chip coupled to the chip stack structure,

wherein the first memory chip comprises a first command decoder circuit, a first terminal to receive a first clock signal, a second terminal coupled to the first command decoder circuit, and a plurality of first memory cells,

wherein the second memory chip comprises a second command decoder circuit, a third terminal to receive a second clock signal, a fourth terminal coupled to the second command decoder circuit, a fifth terminal, and a plurality of second memory cells,

wherein the second terminal of the first memory chip is electrically pled to the fifth terminal of the second memory chip, and

wherein the interface chip comprises sixth, seventh, and eighth terminals respectively electrically coupled to the third, fourth and fifth terminals of the second memory chips.

7. The apparatus of claim 6 , wherein the interface chip comprises an oscillator to produce an oscillation signal at the sixth terminal, and wherein the first terminal of the first chip is electrically coupled to the third terminal of the second chip.

8. The apparatus of claim 6 , wherein the interface chip comprises a ninth terminal and an oscillator to respectively produce a first oscillation signal at the sixth terminal and a second oscillation signal at the ninth terminal, and wherein the second chip comprises a tenth terminal electrically coupled to the ninth terminal of the interface chip and the first terminal of the first chip.

9. The apparatus of claim 7 ,

wherein the first memory cells are refreshed in response to the first clock signal at the first terminal when the first command decoder circuit receives a first refresh command, and

wherein the second memory cells are refreshed in response to the second clock signal at the third terminal when the second command decoder circuit receives a second refresh command.

10. An apparatus, comprising:

a chip stack structure comprising a first memory chip and a second memory chip stacked over the first memory chip;

an interface chip coupled to the chip stack structure, wherein the interface chip is configured to generate a clock signal and to transfer the clock signal to both of the first memory chip and the second memory chip, and to independently transfer a first command signal to the first memory chip to facilitate a first data refresh operation on the first memory chip, and a second command signal to the second memory chip to facilitate a second data refresh operation on the second memory chip;

a first delay circuit introducing a first delay of the clock signal utilized for the first refresh operation on the first memory chip relative to the clock signal generated on the interface chip; and

a second delay circuit introducing a second delay of the clock signal utilized for the second refresh operation on the second memory chip relative to the clock signal generated on the interface chip, wherein each of the first and second delay circuits is located on the interface chip.

11. The apparatus of claim 10 , wherein the first delay circuit is located on the first memory chip; and wherein the second delay circuit is located on the second memory chip.

12. A method, comprising:

generating an original clock signal on an interface chip through use of an oscillator on the interface chip, wherein the interface chip is coupled to a chip stack structure comprising a first memory chip and a second memory chip stacked over the first memory chip;

activating the oscillator in response to a reset signal received by the interface chip;

establishing a first clock signal for use by the first memory chip, the first clock signal based on the original clock signal;

establishing a second clock signal for use by the second memory chip, the second clock signal based on the original clock signal;

transferring a first command signal from the interface chip to the first memory chip to facilitate performing a first data refresh operation on the first memory chip through use of the first clock signal; and

transferring a second command signal from the interface chip to the second memory chip to facilitate performing of a second data refresh operation on the second memory chip through use of the second clock signal.

13. The method of claim 12 ,

wherein the first clock signal is delayed by a first interval relative to the original clock signal; wherein the second clock signal is delayed by a second interval relative to the original clock signal; and

wherein the first interval is different from the second interval.

14. The method of claim 13 ,

wherein the original clock signal is communicated to each of the first memory chip and the second memory chip;

wherein the original clock signal is delayed on the first memory chip to establish the first clock signal; and

wherein the original clock signal is delayed on the second memory chip to establish the second clock signal.

15. The method of claim 12 , wherein the interface chip is stacked with the chip stack structure.