Memory devices and systems with parallel impedance adjustment circuitry and methods for operating the same

1. A memory device, comprising:

first impedance adjustment circuitry configured to provide a first impedance to a received clock signal having a clock impedance; and

second impedance adjustment circuitry configured to provide a second impedance to the received clock signal;

wherein the first impedance adjustment circuitry and the second impedance adjustment circuitry include impedance detection circuitry configured to detect the clock impedance, and

wherein the first impedance and the second impedance are configured to provide a combined impedance based at least in part on the detected clock impedance.

2. The memory device of claim 1 , wherein the combined impedance is equivalent to the clock impedance when the first impedance adjustment circuitry and the second impedance adjustment circuitry are connected to the received clock signal and in parallel with each another.

3. The memory device of claim 1 , wherein the first impedance and the second impedance are both greater than the clock impedance.

4. The memory device of claim 1 , wherein the first impedance adjustment circuitry and the second impedance adjustment circuitry include impedance multiplier circuitry configured to generate the first impedance as a multiple of the clock impedance.

5. The memory device of claim 1 , wherein the first impedance is equivalent to the second impedance.

6. The memory device of claim 1 , wherein the received clock signal is a data clock signal.

7. The memory device of claim 1 , further comprising:

a first terminal coupled to the first impedance adjustment circuitry and configured to receive the clock signal; and

a second terminal coupled to the second impedance adjustment circuitry and configured to receive the clock signal.

8. The memory device of claim 1 , wherein the received clock signal is a differential clock signal comprising a first clock signal and a complimentary second clock signal.

9. The memory device of claim 1 , wherein a single semiconductor die comprises the first impedance adjustment circuitry and the second impedance adjustment circuitry.

10. The memory device of claim 1 , wherein a first semiconductor die comprises the first impedance adjustment circuitry and a second semiconductor die comprises the second impedance adjustment circuitry.

11. The memory device of claim 1 , wherein the memory device is a dynamic random access memory (DRAM) device.

12. A memory system, comprising:

a first memory device including first impedance adjustment circuitry configured to provide a first impedance to a received clock signal having a clock impedance; and

a second memory device including second impedance adjustment circuitry configured to provide a second impedance to the received clock signal;

wherein the first impedance adjustment circuitry and the second impedance adjustment circuitry include impedance detection circuitry configured to detect the clock impedance, and

wherein the first impedance and the second impedance are configured to provide a combined impedance equivalent to the detected clock impedance when the first impedance adjustment circuitry and the second impedance adjustment circuitry are connected to the received clock signal in parallel.

13. The memory system of claim 12 , wherein the first impedance and the second impedance are both greater than the clock impedance.

14. The memory system of claim 12 , wherein the first impedance adjustment circuitry and the second impedance adjustment circuitry include impedance multiplier circuitry configured to generate the first impedance as a multiple of the clock impedance.

15. The memory system of claim 12 , wherein the first impedance is equivalent to the second impedance.

16. The memory system of claim 12 , wherein the received clock signal is a data clock signal.

17. The memory system of claim 12 , wherein:

the first memory device further includes third impedance adjustment circuitry configured to provide a third impedance to the received clock signal;

the second memory device further includes fourth impedance adjustment circuitry configured to provide a fourth impedance to the received clock signal; and

the first impedance, the second impedance, the third impedance and the fourth impedance are configured to provide the combined impedance equivalent to the clock impedance when the first impedance adjustment circuitry, the second impedance adjustment circuitry, the third impedance adjustment circuitry and the fourth impedance adjustment circuitry are connected to the received clock signal in parallel.

18. The memory system of claim 17 . wherein the first impedance, the second impedance, the third impedance and the fourth impedance are each equivalent to one another.

19. The memory system of claim 17 , wherein at least one of the first impedance, the second impedance, the third impedance or the fourth impedance is different than at least one of the first impedance, the second impedance, the third impedance or the fourth impedance.

20. A method comprising:

receiving a clock signal having a clock impedance at a first clock terminal of a first memory device;

receiving the clock signal having the clock impedance at a second clock terminal of a second memory device;

detecting the clock impedance at the first clock terminal and at the second clock terminal; and

adjusting a first impedance at the first clock terminal and a second impedance at the second clock terminal to provide a combined impedance that is based at least in part on the detected clock impedance.

21. The method of claim 20 , wherein the first impedance and the second impedance are both greater than the clock impedance.

22. The method of claim 20 , wherein the first impedance is equivalent to the second impedance.

23. The method of claim 20 , wherein the received clock signal is a data clock signal.

24. The method of claim 20 , wherein the received clock signal is a differential clock signal comprising a first clock signal and a complimentary second clock signal.