IP Library Granted Patent US 10,846,165
Granted Patent B2
US 10,846,165 · App. 15/982,653 · Granted Nov 24, 2020

Adaptive scan frequency for detecting errors in a memory system

Inventors: Kevin R. Brandt (Boise, ID); William C. Filipiak (Boise, ID); Michael G. McNeeley (Boise, ID); Kishore K. Muchherla (Fremont, CA); Sampath K. Ratnam (Boise, ID); Akira Goda (Boise, ID); Todd A. Marquart (Boise, ID)
Assignee: Micron Technology, Inc.
G06F11/079G06F11/0727G06F11/0751G11C29/10
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Quick Facts
Patent No.
US 10,846,165
App. No.
15/982,653
Granted
Nov 24, 2020
Kind
B2
Abstract

Performing a first set of scans on a memory device in a memory system with a first time interval between each scan of the first set of scans to detect errors on the memory device, determining, from performing the first set of scans, that a rate of errors being detected on the memory device is changing, and performing a second set of scans with a second time interval between each scan of the second set of scans to detect errors on the memory device, in response to determining that the rate of errors being detected on the memory device is changing, wherein the second time interval is different than the first time interval.

Claims (37)

1. A method, comprising:

performing a first set of scans on a memory device in a memory system with a first time interval between each scan of the first set of scans to detect errors on the memory device;

determining, from performing the first set of scans, a first rate of errors as a ratio of errors detected to a first number of scans of the first set of scans and a second rate of errors as a ratio of errors detected to a second number of scans of the first set of scans;

determining, from performing the first set of scans, that a rate of errors being detected on the memory device is changing by comparing the first rate of errors to the second rate of errors; and

performing a second set of scans with a second time interval between each scan of the second set of scans to detect errors on the memory device, in response to determining, from performing the first set of scans, that the rate of errors being detected on the memory device is changing, wherein the second time interval is different than the first time interval.

2. The method of claim 1 , wherein the second time interval is less than the first time interval, in response to determining that the rate of errors being detected on the memory device is changing with increasing frequency.

3. The method of claim 1 , wherein the second time interval is greater than the first time interval, in response to determining that the rate of errors being detected on the memory device is changing with decreasing frequency.

4. The method of claim 1 , wherein performing the second set of scans comprises performing the second set of scans with the second time interval on a section of the memory device.

5. The method of claim 1 , wherein the first set of scans is performed with the first time interval on a section of the memory device and the second set of scans is performed with the second time interval on a different section of the memory device.

6. The method of claim 1 , further comprising:

determining that the rate of errors that are being detected on a section of the memory device meets a threshold; and

retiring the section of the memory device in response to determining that a rate of errors that are being detected on the section meets the threshold.

7. The method of claim 1 , further comprising:

adjusting trim settings for the memory device in response to determining that the rate of errors being detected on the memory device is changing.

8. The method of claim 1 , wherein the memory system is a solid-state drive.

9. A system, comprising:

a memory device; and

a processing device coupled to the memory device, wherein the processing device is configured to:

perform a first number of scans with a first time interval between each of the first number of scans to detect errors on the memory device;

detect a rate of errors as a ratio of errors detected to the first number of scans; and

perform a second number of scans with a second time interval between each of the second number of scans to detect errors on the memory device, in response to detecting that the rate of errors being detected on the memory device meets a threshold.

10. The system of claim 9 , wherein the second time interval is less than the first time interval, in response to detecting that the rate of errors being detected on the memory device is changing with increasing frequency.

11. The system of claim 9 , wherein the second time interval is greater than the first time interval, in response to detecting that the rate of errors being detected on the memory device is changing with decreasing frequency.

12. The system of claim 9 , wherein the processing device is further configured to perform the second number of scans in a section of the memory device, in response to detecting that a rate of errors being detected on the section of the memory device meets the threshold.

13. The system of claim 9 , wherein the first set of scans is performed with the first time interval on a section of the memory device and the second set of scans is performed with the second time interval on a different section of the memory device.

14. The system of claim 9 , wherein the processing device is further configured to retire a section of the memory device, in response to detecting that a rate of errors that are being detected on the section meets a threshold.

15. The system of claim 9 , wherein the processing device is further configured to adjust trim settings for the memory device, in response to detecting that the rate of errors being detected on the memory device is changing.

16. The system of claim 9 , wherein the system is a solid-state drive.

17. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:

perform a first set of scans on a memory device in a memory system with a first time interval between each scan of the first set of scans to detect errors on the memory device;

determine, from performing the first set of scans, a first rate of errors as a ratio of errors detected to a first number of scans of the first set of scans and a second rate of errors as a ratio of errors detected to a second number of scans of the first set of scans;

determine, from performing the first set of scans, that a rate of errors being detected on the memory device is changing by comparing the first rate of errors to the second rate of errors; and

perform a second set of scans with a second time interval between each scan of the second set of scans to detect errors on the memory device, in response to determining, from performing the first set of scans, that the rate of errors being detected on the memory device is changing, wherein the second time interval is different than the first time interval.

18. The non-transitory computer-readable storage medium of claim 17 , wherein the second time interval is less than the first time interval, in response to determining that the rate of errors being detected on the memory device is changing with increasing frequency, and the second time interval is greater than the first time interval, in response to determining that the rate of errors being detected on the memory device is changing with decreasing frequency.

19. The non-transitory computer-readable storage medium of claim 17 , wherein the first set of scans is performed with the first time interval on a section of the memory device and the second set of scans is performed with the second time interval on a different section of the memory device.

20. The non-transitory computer-readable storage medium of claim 17 , wherein the processing device is further configured to:

adjust trim settings for the memory device in response to determining that the rate of errors being detected on the memory device is changing.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 11, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050713/0001 →
SUPPLEMENT NO. 9 TO PATENT SECURITY AGREEMENT Recorded Aug 9, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 047282/0463 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 17, 2018
From: BRANDT, KEVIN R.; FILIPIAK, WILLIAM C.; MCNEELEY, MICHAEL G.; RATNAM, SAMPATH K.; GODA, AKIRA; MARQUART, TODD A.; MUCHHERLA, KISHORE K.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 045837/0001 →
Continuity (1)
Related Publication 20190354421A1 · Nov 21, 2019
Cited By (1)
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