Resistive memory cell structures and methods
View Patent ↗Resistive memory cell structures and methods are described herein. One or more memory cell structures comprise a first resistive memory cell comprising a first resistance variable material and a second resistive memory cell comprising a second resistance variable material that is different than the first resistance variable material.
1. A method of forming an array of resistive memory cells, the method comprising:
forming an uninterrupted covering of conductive material in a first and a second region of the array;
forming a first resistance variable material in the first and the second regions on the uninterrupted covering of conductive material;
forming a first cap material in the first and the second regions on the first resistance variable material;
removing the first resistance variable material and the first cap material from the second region;
forming a second resistance variable material on the first cap material of the first region and on the uninterrupted covering of the conductive material of the second region;
forming a second cap material in the first and second regions on the second resistance variable material;
removing the second resistance variable material and the second cap material from the first region; and
forming separate cell stacks corresponding to a respective first and second number of resistive memory cells,
wherein forming the separate cell stacks comprises:
removing portions of the uninterrupted covering of the conductive material from the first region and the second region;
removing a portion of the first resistance variable material from the first region;
removing a portion of the first cap material from the first region;
removing a portion of the second resistance variable material from the second region; and
removing a portion of the second cap material from the second region.
2. The method of claim 1 , wherein forming the array comprises:
forming the first number of resistive memory cells in the first region of the array, the first number of cells comprising the first resistance variable material; and
forming the second number of resistive memory cells in the second region of the array, the second number of cells comprising the second resistance variable material that is different than the first resistance variable material.
3. The method of claim 1 , wherein the first and second cap materials serve as bit lines for the respective first and second number of resistive memory cells.
4. The method of claim 2 , wherein the first and second resistance variable materials include different chalcogenide alloys.
5. The method of claim 1 , further comprising:
forming the first resistance variable material having a first electrothermal property on the uninterrupted covering of the conductive material; and
forming the second resistance variable material having a second electrothermal property different than the first electrothermal property on the first cap material of the first region and on the uninterrupted covering of the conductive material of the second region.
6. The method of claim 1 , further comprising removing the first resistance variable material and the first cap material from the second region via an etch process.
7. The method of claim 1 , further comprising removing the second resistance variable material and the second cap material from the first region via an etch process.
8. The method of claim 1 , further comprising forming the uninterrupted covering of the conductive material over a dielectric material and a plurality of conductive plugs in each of the first region and the second region.