IP Library Granted Patent US 11,509,214
Granted Patent B2
US 11,509,214 · App. 15/963,909 · Granted Nov 22, 2022

Apparatuses and methods for controlling charge pump circuits

Inventor: Takamasa Suzuki (Hachioji, JP)
Assignee: Micron Technology, Inc.
H02M3/07
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Quick Facts
Patent No.
US 11,509,214
App. No.
15/963,909
Granted
Nov 22, 2022
Kind
B2
Abstract

An apparatus and a method that provide a bias voltage to a charge pump circuit are described. An example apparatus includes: a bias voltage generator that receives a first voltage and provides a second voltage responsive to the first voltage; a charge pump circuit that receives an input signal and provides the first voltage. The charge pump circuit includes an inverter and a bias transistor. The inverter receives the input signal and provides a third voltage. The bias transistor coupled between a power node having a power supply voltage and a slew rate driver of the inverter. The bias transistor receives the second voltage and provides a power supply voltage to the slew rate driver responsive to the second voltage less than a threshold voltage and stops providing the power supply voltage to the slew rate driver responsive to the second voltage greater than the threshold voltage.

Claims (27)

1. An apparatus comprising:

a bias voltage generator configured to receive a first voltage and further configured to provide a second voltage responsive to the first voltage;

a first ring oscillator configured to provide a first clock signal and a first complementary clock signal;

a second ring oscillator configured to provide a second clock signal and a second complementary clock signal, the second ring oscillator configured to activate in response to an enable signal;

a first set of charge pump circuits coupled to the first ring oscillator and comprising a first charge pump circuit and a second charge pump circuit different from the first charge pump circuit, wherein the first charge pump circuit receives of the first clock signal, and the second charge pump circuit receives the first complementary signal; and

a second set of charge pump circuits coupled to the second ring oscillator and comprising a third charge pump circuit and a fourth charge pump circuit, wherein the third charge pump circuit receives the second clock signal, and the fourth charge pump circuit receives the second complementary signal, the second set of charge pump circuits and the first set of charge pump circuits being coupled in parallel to an output node that is configured to provide the first voltage,

wherein each charge pump circuit is configured to receive the second voltage from the bias voltage generator,

wherein each charge pump circuit is configured to receive an input signal and further configured to provide the first voltage, each charge pump circuit including:

an inverter including a first slew rate driver and a second slew rate driver coupled to the first slew rate driver at a first node, the inverter configured to receive the input signal and further configured to provide a third voltage; and

a bias transistor coupled between a power node having a first power supply voltage and the first slew rate driver,

wherein the bias transistor is configured to receive the second voltage and further configured to provide a current to the first slew rate driver responsive to the second voltage,

wherein the second slew rate driver is configured to receive a second power supply voltage that is less than the first power supply voltage,

wherein the first slew rate driver is configured to provide the third voltage to the first node responsive to the input signal at the first logic level, wherein the third voltage is the first power supply voltage when the second voltage is less than a threshold voltage and wherein the third voltage is a third power supply voltage between the first power supply voltage and the second power supply voltage when the second voltage is greater than the threshold voltage, and

wherein the second slew rate driver is configured to provide the second power supply voltage as the third voltage to the first node responsive to the input signal at the second logic level different from the first logic level.

2. The apparatus of claim 1 , wherein the second voltage is continuous.

3. The apparatus of claim 2 , wherein the bias voltage generator is configured to receive a reference voltage, and further configured to detect an amplitude of voltage fluctuations in the first voltage with reference to the reference voltage and provide the second voltage.

4. The apparatus of claim 2 , wherein the bias voltage generator is configured to increase the second voltage responsive to a decrease of the amplitude of voltage fluctuations and further configured to decrease the second voltage responsive to an increase of the amplitude of voltage fluctuations, and

wherein the current is larger responsive to a decrease of the second voltage and the current is smaller responsive to an increase of the second voltage.

5. The apparatus of claim 1 , wherein each charge pump circuit further comprises:

a capacitor having a first end coupled to the first node and a second end coupled to a second node;

a first switch coupled between the second node and the power node, and configured to provide the first power supply voltage to the second node responsive to a fifth voltage at the second node; and

a second switch configured to provide the fifth voltage as the first voltage responsive to the fifth voltage,

wherein the capacitor is configured to increase the fifth voltage greater than the first power supply voltage responsive to the third voltage.

6. The apparatus of claim 1 , wherein the first charge pump circuit and the second charge pump circuit are coupled in parallel to the output node that is configured to provide the first voltage.

7. The apparatus of claim 1 , wherein the first charge pump circuit and the second charge pump circuit are coupled in serial, and

wherein the first charge pump circuit is coupled to an output node that is configured to provide the first voltage.

8. The apparatus of claim 1 , wherein each charge pump circuit is a switched capacitor.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 11, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050713/0001 →
SUPPLEMENT NO. 9 TO PATENT SECURITY AGREEMENT Recorded Aug 9, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 047282/0463 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 26, 2018
From: SUZUKI, TAKAMASA
To: MICRON TECHNOLOGY, INC.
Reel/Frame 045649/0912 →
Continuity (1)
Related Publication 20190334432A1 · Oct 31, 2019