Floating gate memory cells in vertical memory

1. A memory array, comprising:

multiple strings of memory cells separated by alternating dielectrics separating each memory cell in the string by a respective alternating dielectric from an adjacent memory cell in the string,

wherein a memory cell string includes,

a respective channel material forming a channel for memory cells of the string, and

wherein each memory cell of the string comprises,

a control gate extending between a first alternating dielectric and a second alternating dielectric,

a floating gate extending between the first alternating dielectric and the second alternating dielectric, the floating gate including a first portion and a second portion extending from the first portion, wherein the first portion contacts each of the first and second alternating dielectrics, and

a charge blocking structure between the floating gate and the control gate, a portion of the charge blocking structure extending between the second portion and the first and second alternating dielectrics; and

a tunnel dielectric between the first portion of the floating gates of the memory cells of the string and the channel material.

2. The memory array of claim 1 , wherein the charge blocking structure includes a barrier material positioned at least partially between a first charge blocking material and a second charge blocking material.

3. The memory array of claim 2 , wherein the barrier material comprises nitride and wherein each of the first and second charge blocking materials comprise oxide.

4. The memory array of claim 2 , wherein the second charge blocking material completely separates the barrier material from the floating gate.

5. The memory array of claim 2 , wherein the floating gate is in contact with the barrier material and the second charge blocking material.

6. The memory array of claim 5 , wherein each of the barrier material and the second charge blocking material are in contact with the first portion of the floating gate.

7. A memory array, comprising:

multiple strings of memory cells, the memory cells in the string separated by alternating dielectrics separating each memory cell in the string by a respective alternating dielectric from an adjacent memory cell in the string,

wherein each memory cell string includes,

a respective channel material forming a channel for memory cells of the string, and

wherein each memory cell of a string comprises,

a control gate extending between first alternating dielectric at a first surface of the memory cell and a second alternating dielectric at a second surface of the memory cell;

a floating gate extending between the first alternating dielectric and the second alternating dielectric, the floating gate including a first portion and a second portion,

wherein the first portion has a first dimension along the direction of current flow through the channel material, the first portion contacting each of the first and second alternating dielectrics,

wherein the second portion extends from the first portion toward the control gate, and

wherein the second portion has a second dimension along the direction of current flow through the channel material that is less than the first dimension;

a third dielectric between the second portion of the floating gate and the control gate, a portion of the third dielectric extending between the second portion and at least one of the first and second alternating dielectrics; and

a fourth dielectric between the first portion of the floating gate and the channel material.

8. The memory array of claim 7 ,

wherein the third dielectric comprises a barrier film and first and second oxides;

wherein the floating gate is separated from the barrier film by at least one of the first and second oxides; and

wherein one of the first and second oxides extends between the second portion of the floating gate and at least one of the first and second alternating dielectrics.

9. The memory array of claim 7 , wherein a portion of the barrier film extends around at least a portion of the second portion of the floating gate.

10. The memory array of claim 7 , wherein the control gate contacts each of the first and second alternating dielectrics, and wherein the control gate has a third dimension extending in the direction of current flow through the channel material.

11. The memory array of claim 10 , wherein the third dimension of the control gate is substantially equal to the first dimension of the first portion of the floating gate.

12. The memory array of claim 7 , wherein the first and second surfaces of the memory cell are opposite one another.

13. The memory array of claim 7 , wherein the fourth dielectric comprises a tunnel oxide.

14. A memory array, comprising:

multiple strings of memory cells, separated by alternating dielectrics, separating each memory cell in the string by a respective alternating dielectric from an adjacent memory cell in the string,

wherein each memory cell string includes,

a respective channel material forming a channel for memory cells of the string, and

wherein each memory cell of a memory cell string includes,

a control gate extending between a first alternating dielectric at a first surface of the memory cell and a second alternating dielectric at a second surface of the memory cell;

a floating gate extending between the first alternating dielectric and the second alternating dielectric, the floating gate including a first portion and a second portion,

wherein the first portion has a first dimension along the direction of current flow through the channel material, and wherein the first portion contacts each of the first and second alternating dielectrics, and

wherein the second portion has a second dimension along the direction of current flow through the channel material that is less than the first dimension to form a protrusion extending from the first portion toward the control gate;

a third dielectric between the second portion of the floating gate and the control gate, a portion of the third dielectric extending between the second portion and at least one of the first and second alternating dielectrics; and

a fourth dielectric between the first portion of the floating gate and the channel material.

15. The memory array of claim 14 , wherein the third dielectric includes a barrier material positioned at least partially between a first charge blocking material and a second charge blocking material.

16. The memory array of claim 15 , wherein the barrier material comprises nitride and wherein each of the first and second charge blocking materials comprise oxide.

17. The memory array of claim 15 , wherein the second charge blocking material completely separates the barrier material from the floating gate.

18. A memory array, comprising:

multiple strings of memory cells, separated by alternating dielectrics, separating each memory cell in the string by a respective alternating dielectric from an adjacent memory cell in the string,

wherein each memory cell string includes,

a respective channel material forming a channel for memory cells of the string, and

wherein each memory cell of a memory cell string includes,

a control gate extending between first alternating dielectric at a first surface of the memory cell and a second alternating dielectric at a second surface of the memory cell;

a floating gate extending between the first alternating dielectric and the second alternating dielectric, the floating gate including a first portion and a second portion,

wherein the first portion has a first dimension along the direction of current flow through the channel material,

wherein the second portion has a second dimension along the direction of current flow through the channel material that is less than the first dimension to form a protrusion extending from the first portion toward the control gate;

a third dielectric between the second portion of the floating gate and the control gate, a portion of the third dielectric extending between the second portion and at least one of the first and second alternating dielectrics, wherein the third dielectric includes a barrier material positioned at least partially between a first charge blocking material and a second charge blocking material, and wherein the floating gate is in contact with the barrier material and the second charge blocking material; and

a fourth dielectric between the first portion of the floating gate and the channel material.

19. The memory array of claim 18 , wherein each of the barrier material and the second charge blocking material are in contact with the first portion of the floating gate.