Prefetch signaling in memory system or sub-system
Methods, systems, and devices for prefetch signaling in a memory system or sub-system are described. A memory device (e.g., a local memory controller of memory device) of a main memory may transmit a prefetch indicator indicating a size of prefetch data associated with a first set of data requested by an interface controller. The size of the prefetch data may be equal to or different than the size of the first set of data. The main memory may, in some examples, store the size of prefetch data along with the first set of data. The memory device may transmit the prefetch indicator (e.g., an indicator signal) to the interface controller using a pin compatible with an industry standard or specification and/or a separate pin configured for transmitting command or control information. The memory device may transmit the prefetch indicator while the first set of data is being transmitted.
1. A method, comprising:
receiving, from a controller, a read command for a first set of data;
identifying, in response to the read command, an indicator associated with the first set of data that indicates a size of a second set of data to be transmitted in response to the read command for the first set of data;
transmitting, to the controller, a portion of the second set of data along with an indication of the size of the second set of data, wherein the size of the second set of data is greater than a size of the portion of the second set of data;
determining that at least a subset of the second set of data is unavailable in an open page of a memory array comprising non-volatile memory cells; and
transmitting, to the controller, a second indication of a time delay for at least the subset of the second set of data.
2. The method of claim 1 , wherein transmitting the indication along with the portion of the second set of data comprises:
transmitting the indication concurrently with at least a subset of the portion of the second set of data.
3. The method of claim 1 , wherein the indication comprises at least one bit in the memory array, and wherein the memory array stores the portion of the second set of data.
4. The method of claim 1 , further comprising:
determining that a second portion of the second set of data is available in the open page of the memory array; and
transmitting, to the controller, the second portion of the second set of data after transmitting the portion of the second set of data.
5. The method of claim 1 , wherein identifying the indicator comprises:
reading a first set of memory cells in the memory array, the first set of memory cells having a faster nominal access speed than a second set of memory cells in the memory array, the second set of memory cells storing the first set of data; and
identifying a value of at least one bit in the first set of memory cells.
6. The method of claim 1 , further comprising:
receiving, from the controller, an instruction to update the indicator, the instruction being based at least in part on an access pattern associated with the first set of data; and
updating, in the memory array that stores the indicator and the first set of data, a value of the indicator based at least in part on the instruction.
7. A method, comprising:
receiving, from a controller, a read command for a first set of data;
identifying, in response to the read command, an indicator associated with the first set of data that indicates a size of a second set of data to be transmitted in response to the read command for the first set of data; and
transmitting, to the controller, a portion of the second set of data along with an indication of the size of the second set of data, wherein the size of the second set of data is greater than a size of the portion of the second set of data, wherein transmitting the indication along with the portion of the second set of data comprises:
transmitting the indication via a first pin coupled with a memory array and designated for command or control information, the memory array storing the indicator and the second set of data; and
transmitting the portion of the second set of data via a second pin coupled with the memory array.
8. The method of claim 7 , wherein the first pin is configured for transmitting at least one of data mask/inversion (DMI) information, link error correction code (ECC) parity information, or status information regarding the memory array, or any combination thereof.
9. A method, comprising:
transmitting, to a memory device, a read command for a first set of data of a first size;
receiving, from the memory device, a portion of a second set of data and an indicator of a second size of the second set of data, the second set of data including the first set of data;
determining that the second size of the second set of data is greater than the first size based at least in part on the indicator;
receiving a remainder of the second set of data based at least in part on determining that the second size of the second set of data is greater than the first size; and
receiving, from the memory device, a second indicator that indicates a latency for at least a subset of the remainder of the second set of data.
10. The method of claim 9 , wherein receiving the portion of the second set of data and the indicator comprises:
receiving the indicator concurrently with at least one bit included in the portion of the second set of data.
11. The method of claim 9 , further comprising:
transmitting at least the first set of data to a buffer based at least in part on determining the second size of the second set of data, wherein the portion comprises the first set of data.
12. The method of claim 9 , further comprising:
transmitting, to the memory device after a time duration associated with the latency, a subsequent read command for at least the subset of the remainder of the second set of data.