Error correction code event detection
Methods, systems, and devices for operating a memory cell or cells are described. An error in stored data may be detected by an error correction code (ECC) operation during sensing of the memory cells used to store the data. The error may be indicated in hardware by generating a measurable signal on an output node. For example, the voltage at the output node may be changed from a first value to a second value. A device monitoring the output node may determine an error has occurred for a set of data based at least in part on the change in the signal at the output node.
1. An electronic memory apparatus, comprising:
a memory array comprising a plurality of memory cells;
an error correction code (ECC) array in electronic communication with the memory array and operable to detect a first error associated with a first set of cells of the plurality of memory cells and detect a second error associated with a second set of memory cells of the plurality of memory cells;
a first latch in electronic communication with the ECC array and operable to change an output state based on corrected data received from the ECC array;
a second latch in electronic communication with the ECC array and operable to change an output state based at least in part on the first error associated with the corrected data;
an output pin in electronic communication with the second latch, wherein a voltage measurable at the output pin is based at least in part on the output state of the second latch and indicates that there is the first error associated with the corrected data; and
circuitry in electronic communication with the output pin and operable to maintain the voltage measurable on the output pin irrespective of the detection of the second error.
2. The electronic memory apparatus of claim 1 , further comprising:
a user interface in electronic communication with the memory array.
3. The electronic memory apparatus of claim 2 , wherein an output of the user interface is connected to an input of the second latch, and wherein the user interface is operable to enable the second latch.
4. The electronic memory apparatus of claim 1 , further comprising:
a transistor in electronic communication with the output pin, wherein the transistor comprises a drain that is connected to the output pin.
5. The electronic memory apparatus of claim 4 , further comprising:
a resistor in electronic communication with the drain, wherein the resistor is electronic communication with a plurality of packages, and wherein at least one package of the plurality of packages houses the memory array.
6. The electronic memory apparatus of claim 1 , wherein the circuitry is in electronic communication with the second latch operable to generate the voltage measurable at the output pin based on the output state of the second latch.
7. The electronic memory apparatus of claim 1 , further comprising:
a memory controller in electronic communication with the memory array and operable to select and deselect a set of memory cells, wherein the corrected data is associated with the set of memory cells; and wherein
the circuitry is in electronic communication with the memory controller and operable to modify the voltage measurable at the output pin based at least in part on deselection of the set of memory cells.
8. The electronic memory apparatus of claim 1 , wherein the first error is detected by the ECC array, and further comprising:
a timing component in electronic communication with the ECC array, the timing component operable to determine when a threshold amount of time has elapsed since the first error was detected; and wherein
the circuitry is in electronic communication with the timing component and operable to modify the voltage measurable at the output pin based at least in part on the determination that the threshold amount of time has elapsed since the first error was detected.