Boosted high-speed level shifter
View Patent ↗Methods, systems, and devices for shifting voltage levels of electrical signals and more specifically for boosted high-speed level shifting are described. A boosted level shifter may include a driver circuit that generates a drive signal having a greater voltage swing than an input signal, and the drive signal may drive the gate of a pull-up transistor within the boosted level shifter. The lower bound of the drive signal may in some cases be a negative voltage. Driving the pull-up transistor with a drive signal having a greater voltage swing than the input signal may improve the operational speed and current-sourcing capability of the pull-up transistor, which may provide speed and efficiency benefits.
1. An apparatus, comprising:
a level shifter configured to convert an input signal having a first voltage swing from a non-negative voltage to a positive voltage into an output signal having a second voltage swing that is greater than the first voltage swing, the level shifter comprising:
a driver circuit configured to generate a drive signal based at least in part on the input signal, the drive signal having a third voltage swing that is greater than the first voltage swing, wherein the third voltage swing is from a negative voltage to the positive voltage; and
a first pull-up transistor configured to drive the output signal when the input signal is in a first state, wherein the drive signal drives a gate of the first pull-up transistor; and
a second pull-up transistor configured to drive the output signal when the input signal is in a second state, wherein the input signal drives a gate of the second pull-up transistor.
2. The apparatus of claim 1 , further comprising:
an inverter configured to generate an inverted version of the input signal and drive a source of the second pull-up transistor using the inverted version of the input signal.
3. The apparatus of claim 1 , wherein the driver circuit comprises:
a single pull-up transistor configured to couple the gate of the first pull-up transistor to a voltage source corresponding to an upper bound of the first voltage swing when the input signal is in the second state.
4. The apparatus of claim 3 , wherein:
a source of the single pull-up transistor is coupled with the voltage source corresponding to the upper bound of the first voltage swing; and
a drain of the single pull-up transistor is coupled with the gate of the first pull-up transistor.
5. The apparatus of claim 3 , wherein a drain of the single pull-up transistor is coupled with an n-type transistor.
6. The apparatus of claim 5 , wherein the n-type transistor comprises a triple well transistor.
7. The apparatus of claim 3 , wherein:
the single pull-up transistor has a first gate oxide thickness; and
at least one other transistor within the driver circuit has a second gate oxide thickness that is less than the first gate oxide thickness.
8. The apparatus of claim 1 , wherein the driver circuit comprises:
a switching network configured to generate a voltage differential across a boost capacitor when the input signal is in the second state and couple the boost capacitor with the gate of the first pull-up transistor when the input signal is in the first state.
9. The apparatus of claim 8 , wherein the voltage differential is based at least in part on the first voltage swing.
10. The apparatus of claim 8 , wherein the switching network is further configured to couple the boost capacitor with a voltage source corresponding to a lower bound of the first voltage swing when the input signal is in the second state.
11. The apparatus of claim 8 , wherein:
the boost capacitor comprises a transistor; and
a capacitance of the boost capacitor comprises a gate capacitance of the transistor.
12. The apparatus of claim 1 , wherein:
being in the first state comprises having a voltage above a first threshold voltage; and
being in the second state comprises having a voltage below a second threshold voltage.
13. The apparatus of claim 12 , wherein:
the first threshold voltage corresponds to a first logic value; and
the second threshold voltage corresponds to a second logic value.
14. The apparatus of claim 1 , wherein:
the second voltage swing is from a negative voltage to the positive voltage.
15. A method, comprising:
receiving an input signal having a first voltage swing from a non-negative voltage to a positive voltage;
generating a drive signal based at least in part on the input signal, the drive signal having a third voltage swing that is greater than the first voltage swing, wherein the third voltage swing is from a negative voltage to the positive voltage; and
generating an output signal having a second voltage swing that is greater than the first voltage swing based at least in part on applying the drive signal to a gate of a first pull-up transistor and the input signal to a gate of a second pull-up transistor.
16. The method of claim 15 , wherein generating the drive signal comprises:
coupling, when the input signal is in a second state, the gate of the first pull-up transistor to a voltage source corresponding to an upper bound of the first voltage swing via a single pull-up transistor.
17. The method of claim 15 , wherein generating the drive signal comprises:
generating a voltage differential across a boost capacitor when the input signal is in a second state; and
coupling the boost capacitor with the gate of the first pull-up transistor when the input signal is in a first state.
18. The method of claim 15 , further comprising:
generating an inverted version of the input signal;
applying the inverted version of the input signal to a source of the second pull-up transistor, wherein generating the output signal is based at least in part on applying the inverted version of the input signal to the source of the second pull-up transistor.
19. An apparatus, comprising:
a level shifter configured to receive an input signal having a first voltage range and generate an output signal having a second voltage range, wherein the first voltage range is from a non-negative lower bound to a positive upper bound and the second voltage range is from a negative lower bound to the positive upper bound, the level shifter comprising:
a first drive transistor configured to couple a gate of a first pull-up transistor with a boost capacitor when the input signal is in a first state, the first pull-up transistor configured to drive the output signal when the input signal is in the first state;
a second drive transistor configured to couple the gate of the first pull-up transistor to a voltage source corresponding to the positive upper bound when the input signal is in a second state, wherein the second drive transistor has a first sate oxide thickness and at least one other transistor within the level shifter has a second sate oxide thickness that is less than the first sate oxide thickness; and
a second pull-up transistor configured to drive the output signal when the input signal is in the second state, wherein the input signal drives a gate of the second pull-up transistor and an inverted version of the input signal drives a source of the second pull-up transistor.