Shifting data in sensing circuitry
View Patent ↗The present disclosure is related to shifting data using sensing circuitry. An example apparatus can include a first sensing component and a second sensing component. The first sensing component can include a first sense amplifier coupled to a first pair of complementary sense lines and a first compute component comprising a number of first pass transistors. The second sensing component can include a second sense amplifier coupled to a second pair of complementary sense lines. The second sensing component can include a second compute component comprising a number of second pass transistors. The first pair of complementary sense lines can be coupled to the number of first pass transistors and the number of second pass transistors.
1. An apparatus, comprising:
a first compute component comprising a number of first pass transistors;
a first pair of complementary sense lines coupled to the first compute component;
a second compute component comprising a number of second pass transistors;
a second pair of complementary sense lines coupled to the second compute component; and
wherein the first pair of complementary sense lines are each directly coupled to a respective one of the number of first pass transistors and directly coupled to a respective one of the number of second pass transistors.
2. The apparatus of claim 1 , wherein the number of first pass transistors are complement pass transistors comprising pass transistors associated with a complement value and the number of second pass transistors are true pass transistors comprising pass transistors associated with a true value.
3. The apparatus of claim 1 , wherein the first pair of complementary sense lines is adjacent to the second pair of complementary sense lines.
4. The apparatus of claim 1 , wherein the first compute component comprises a number of true pass transistors comprising pass transistors associated with a true value.
5. The apparatus of claim 1 , wherein:
the second compute component comprises a number of third pass transistors; and
the second pair of complementary sense lines are each directly coupled to a respective one of the number of third pass transistors.
6. The apparatus of claim 5 , further comprising:
a third compute component comprising a number of fourth pass transistors;
a third pair of complementary sense lines coupled to the third compute component; and
wherein the third pair of complementary sense lines are each directly coupled to a respective one of the number of fourth pass transistors.
7. The apparatus of claim 6 , wherein the third compute component is adjacent to the first compute component opposite the second compute component.
8. The apparatus of claim 7 , wherein the number of third pass transistors comprise a number of complement pass transistors comprising pass transistors associated with a complement value.
9. The apparatus of claim 8 , wherein the second pair of complementary sense lines are directly coupled to the number of complement pass transistors.
10. The apparatus of claim 1 , wherein the second compute component is configured to perform an operation on a true value associated with the first pair of complementary sense lines and a complement value associated with the second pair of complementary sense lines.
11. The apparatus of claim 10 , wherein the number of second pass transistors comprise a pair of true pass transistors comprising pass transistors associated with the true value and a pair of complement pass transistors comprising pass transistors associated with the complement value.
12. The apparatus of claim 10 , wherein the second pass transistors comprise:
a pair of true pass transistors, comprising pass transistors associated with the true value, directly coupled to the first pair of complementary sense lines; and
a pair of complement pass transistors, comprising pass transistors associated with the complement value, directly coupled to the second pair of complementary sense lines.
13. The apparatus of claim 12 , further comprising a controller configured to cause the true value associated with the first pair of complementary sense lines passes through the pair of true pass transistors to transfer the true value from being associated with the first pair of complementary sense lines to being stored in the second compute component.
14. The apparatus of claim 12 , further comprising a controller configured to cause the complement value associated with the second pair of complementary sense lines passes through the pair of complement pass transistors to transfer the complement value from being associated with the second pair of complementary sense lines to being stored in the second compute component.
15. The apparatus of claim 1 , further comprising:
a first pair of memory cells coupled to the first pair of complementary sense lines and to a pair of access lines; and
a second pair of memory cells coupled to the second pair of complementary sense lines and to the pair of access lines.
16. The apparatus of claim 15 , wherein:
a first one of the first pair of memory cells is directly coupled to a first one of the first pair of complementary sense lines;
a second one of the first pair of memory cells is directly coupled to a second one of the first pair of complementary sense lines;
a first one of the second pair of memory cells is directly coupled to the first one of the first pair of complementary sense lines; and
a second one of the second pair of memory cells is directly coupled to the second one of the second pair of complementary sense lines.
17. A method, comprising:
transferring a first value associated with a first pair of complementary sense lines to a compute component directly coupled to the first pair of complementary sense lines and directly coupled to a second pair of complementary sense lines;
transferring a second value associated with the second pair of complimentary sense lines to the compute component; and
performing an operation on the first value and the second value using the compute component.
18. The method of claim 17 , wherein the first value is a true value.
19. The method of claim 18 , wherein the second value is a complement value.
20. The method of claim 17 , wherein performing the operation comprises performing at least one of an AND operation and an OR operation.