IP Library Patent Application 15662204
Patent Application
App. No. 15/662,204

MICROFEATURE WORKPIECES AND METHODS FOR FORMING INTERCONNECTS IN MICROFEATURE WORKPIECES

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Quick Facts
Patent No.
US None
App. No.
15/662,204
Abstract

Methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects are disclosed herein. The microfeature workpieces may have a terminal and a substrate with a first side carrying the terminal and a second side opposite the first side. In one embodiment, a method includes (a) constructing an electrically conductive interconnect extending from the terminal to at least an intermediate depth in the substrate with the interconnect electrically connected to the terminal, and (b) removing material from the second side of the substrate so that a portion of the interconnect projects from the substrate.

Claims (49)

1 . A microfeature workpiece, comprising:

a substrate having a first side and a second side opposite the first side;

a microelectronic die formed in and/or on the substrate, the die including a terminal at the first side of the substrate and an integrated circuit operably coupled to the terminal; and

an electrically conductive interconnect extending from the terminal through the substrate and projecting from the second side of the substrate, wherein the interconnect is electrically coupled to the terminal and has an exposed conductive surface at the end of the interconnect;

a dielectric structure covering the second side of the substrate and having an exterior surface, wherein the exposed surface of the interconnect is not covered by the dielectric structure, and wherein a portion of the interconnect projects from the exterior surface of the dielectric structure.

2 . The microfeature workpiece of claim 1 wherein:

the substrate further comprises a hole;

the electrically conductive interconnect comprises a conductive fill material in the hole and a conductive layer in the hole between the conductive fill material and the substrate;

the conductive fill material and the conductive layer each include an exposed surface; and

the exposed surface of the conductive fill material is recessed relative to the exposed surface of the conductive layer.

3 . The microfeature workpiece of claim 1 , further comprising a layer of parylene disposed on the second side of the substrate.

4 . The microfeature workpiece of claim 1 , further comprising a conductive member formed on the portion of the interconnect projecting from the substrate.

5 . The microfeature workpiece of claim 1 , further comprising a conductive cap formed on the portion of the interconnect projecting from the substrate.

6 . The microfeature workpiece of claim 1 wherein the interconnect projects between approximately 5 and 10 microns from the substrate.

7 . The microfeature workpiece of claim 1 wherein:

the substrate further comprises a hole;

the electrically conductive interconnect comprises a conductive fill material in the hole, a conductive layer in the hole between the conductive fill material and the substrate, and a recess at the second side of the substrate; and

the workpiece further comprises a dielectric material disposed in the recess.

8 . The microfeature workpiece of claim 1 wherein the dielectric structure includes a first dielectric layer on the second side of the substrate and a second dielectric layer on the first dielectric layer, and wherein the second dielectric layer is different than the first dielectric layer.

9 . The microfeature workpiece of claim 8 , wherein the first and second dielectric layers are removable without photolithography.

10 . The microfeature workpiece of claim 8 , wherein the first dielectric layer includes a first material and the second dielectric layer includes a second material, and wherein the first material is removable by a removal process that generally does not affect the second material.

11 . A microfeature workpiece, comprising:

a substrate having a first side and a second side opposite the first side;

a microelectronic die formed in and/or on the substrate, the die including a terminal at the first side of the substrate and an integrated circuit operably coupled to the terminal;

a hole extending through the terminal and the substrate;

a dielectric structure on the second side of the substrate defining a plane; and

an electrically conductive interconnect including a conductive fill material in the hole and a conductive layer in the hole between the conductive fill material and the substrate, both the conductive fill material and the conductive layer being electrically coupled to the terminal and extending from the terminal through the substrate and projecting from the substrate such that the conductive fill material and the conductive layer projects beyond the plane.

12 . The microfeature workpiece of claim 11 wherein:

the conductive fill material and the conductive layer each include an exposed surface; and

the exposed surface of the conductive fill material is recessed relative to the exposed surface of the conductive layer.

13 . The microfeature workpiece of claim 11 wherein:

the conductive fill material and the conductive layer each include an exposed surface;

the exposed surface of the conductive fill material is recessed relative to the exposed surface of the conductive layer such that the conductive fill material and the conductive layer define a recess in the interconnect; and

the dielectric structure further includes a section disposed in the recess.

14 . The microfeature workpiece of claim 11 , further comprising a conductive member formed on the portion of the interconnect that projects from the substrate.

15 . The microfeature workpiece of claim 11 wherein the dielectric structure includes a first dielectric layer on the second side of the substrate and a second dielectric layer on the first dielectric layer, and wherein the second dielectric layer is different than the first dielectric layer.

16 . The microfeature workpiece of claim 15 , wherein the first and second dielectric layers are removable without photolithography.

17 . The microfeature workpiece of claim 15 , wherein the first dielectric layer includes a first material and the second dielectric layer includes a second material, and wherein the first material is removable by a removal process that generally does not affect the second material.

18 . A microfeature workpiece, comprising:

a substrate having a first side and a second side opposite the first side;

a microelectronic die formed in and/or on the substrate, the die including a terminal at the first side of the substrate and an integrated circuit operably coupled to the terminal;

a dielectric structure disposed on the second side of the substrate and having an exterior surface; and

an electrically conductive interconnect including a conductive fill material in the hole and a conductive layer in the hole between the conductive fill material and the substrate, both the conductive fill material and the conductive layer being electrically coupled to the terminal and extending from the terminal through the substrate and projecting from the substrate and the exterior surface, wherein the conductive fill material is recessed relative to the conductive layer at the second side of the substrate.

19 . The microfeature workpiece of claim 18 wherein the conductive fill material and the conductive layer each include an exposed surface.

20 . The microfeature workpiece of claim 18 wherein the dielectric structure includes a section disposed in a recess defined by the conductive fill material and the conductive layer.

21 . The microfeature workpiece of claim 18 , further comprising a conductive member formed on the portion of the interconnect that projects from the substrate.

22 . The microfeature workpiece of claim 18 wherein the dielectric structure includes a first dielectric layer on the second side of the substrate and a second dielectric layer on the first dielectric layer, and wherein the second dielectric layer is different than the first dielectric layer.

23 . The microfeature workpiece of claim 22 , wherein the first and second dielectric layers are removable without photolithography.

24 . The microfeature workpiece of claim 22 , wherein the first dielectric layer includes a first material and the second dielectric layer includes a second material, and wherein the first material is removable by a removal process that generally does not affect the second material.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 11, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050713/0001 →
SUPPLEMENT NO. 9 TO PATENT SECURITY AGREEMENT Recorded Aug 9, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 047282/0463 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →