Adaptive watchdog in a memory device
View Patent ↗Devices and techniques for an adjustable watchdog in a memory device are disclosed herein. A memory operation command is received at a first time with a memory device from a host. A reset signal is received, with the memory device from the host, at a second time following the first time. A time interval between the first time and the second time is measured. A delay interval for a timer in the memory device to reset the memory device independently of receiving a further reset signal from the host is established based on the measured time interval.
1. A method comprising:
receiving, with a memory device at a first time, a memory operation command from a host;
receiving, with the memory device at a second time following the first time, a reset signal from the host;
measuring a time interval between the first time and the second time; and
establishing, based on the measured time interval, a delay interval for a watchdog timer in the memory device to reset the memory device independently of receiving a further reset signal from the host.
2. The method of claim 1 , wherein establishing the watchdog timer delay interval comprises setting the watchdog timer to a value that is less than the time interval.
3. The method of claim 1 , wherein the time interval is a first time interval, further comprising:
measuring multiple time intervals, each of the multiple time intervals representing an amount of time between the memory device receiving a given memory operation command request and the memory device completing the given memory operation command;
identifying the longest of the multiple time intervals as a second time interval; and
establishing the watchdog timer delay interval based on the first and the second time intervals.
4. The method of claim 3 , wherein establishing the watchdog timer delay interval based on the first and the second time intervals comprises:
adjusting the first and second time intervals;
determining a lowest time interval of the adjusted first and second time intervals; and
establishing the watchdog timer delay interval based on the lowest time interval.
5. The method of claim 4 , wherein adjusting the first and second time intervals comprises reducing the first time interval by a first threshold amount and increasing the second time interval by a second threshold amount.
6. The method of claim 5 , wherein at least one of the first and second threshold amounts is determined based on a characteristic of the host.
7. The method of claim 3 , further comprising:
maintaining an index representing latencies associated with different classes of memory operation commands;
setting priorities for each of the different classes of memory operation commands; and
identifying as the second time interval a time interval of the multiple time intervals associated with the memory operation command having the highest priority.
8. The method of claim 1 , further comprising setting the watchdog timer to a default value after a threshold time period or in response to detecting changes to the host.
9. The method of claim 1 , wherein the memory operation command comprises at least one of read, write, program, and erase.
10. A memory device comprising:
a watchdog timer; and
control circuitry configured to:
receive, with the memory device at a first time, a memory operation command from a host;
receive, with the memory device at a second time following the first time, a reset signal from the host;
measure a time interval between the first time and the second time; and
establish, based on the measured time interval, a delay interval for the watchdog timer in the memory device to reset the memory device independently of receiving a further reset signal from the host.
11. The memory device of claim 10 , wherein the control circuitry configured to establish the watchdog timer delay interval is further configured to set the watchdog timer to a value that is less than the time interval.
12. The memory device of claim 10 , wherein the time interval is a first time interval, and wherein the control circuitry is further configured to:
measure multiple time intervals, each of the multiple time intervals representing an amount of time between the memory device receiving a given memory operation command request and the memory device completing the given memory operation command;
identifying the longest of the multiple time intervals as a second time interval; and
establish the watchdog timer delay interval based on the first and the second time intervals.
13. The memory device of claim 12 , wherein the control circuitry is configured to establish the watchdog timer delay interval based on the first and the second time intervals by:
adjusting the first and second time intervals;
determining a lowest time interval of the adjusted first and second time intervals; and
establishing the watchdog timer delay interval based on the lowest time interval.
14. The memory device of claim 13 , wherein the control circuitry is configured to adjust the first and second time intervals by reducing the first time interval by a first threshold amount and increasing the second time interval by a second threshold amount.
15. The memory device of claim 14 , wherein at least one of the first and second threshold amounts is determined based on a characteristic of the host.
16. The memory device of claim 12 , wherein the control circuitry is further configured to:
maintain an index representing latencies associated with different classes of memory operation commands;
set priorities for each of the different classes of memory operation commands; and
identify as the second time interval a time interval of the multiple time intervals associated with the memory operation command having the highest priority.
17. The memory device of claim 10 , wherein the control circuitry is further configured to set the watchdog timer delay interval to a default value after a threshold time period or in response to detecting changes to the host.
18. The memory device of claim 10 , wherein the memory operation command comprises at least one of read, write, program, and erase.