Integrated circuitry and 3D memory

1. Three-D (3D) NAND memory circuitry, comprising:

a memory array circuitry region comprising a repeating array of elevationally extending strings of memory cells;

an adjacent circuitry region immediately laterally adjacent to and contacting one elongated major peripheral side of the memory array circuitry region, the adjacent circuitry region being distinct in structure from the memory array circuitry region where contacting the memory array circuitry region and distinct in operation from the memory array circuitry region; and

the memory array circuitry region and the adjacent circuitry region having a respective longitudinally non-linear edge at an interface relative one another along the one elongated major peripheral side of the memory array circuitry region.

2. The 3D NAND memory circuitry of claim 1 wherein the one major peripheral side of the memory array circuitry region is straight, the memory array circuitry region non-linear edge and the adjacent circuitry region non-linear edge comprise respective longitudinally-straight segments that angle relative to the one straight major peripheral side of the memory array circuitry region and angle longitudinally with immediately longitudinally-adjacent of said longitudinally-straight segments along the one straight major peripheral side of the memory array circuitry region.

3. The 3D NAND memory circuitry of claim 2 wherein the angles of said longitudinally-straight segments relative to the one straight major peripheral side of the memory array circuitry region are within 2.5° of one another along the one straight major peripheral side of the memory array circuitry region.

4. The 3D NAND memory circuitry of claim 2 wherein each of the angles of said longitudinally-straight segments relative to the one straight major peripheral side of the memory array circuitry region is acute.

5. The 3D NAND memory circuitry of claim 4 wherein each of the angles of said longitudinally-straight segments relative to the one straight major peripheral side of the memory array circuitry region is at least 30°.

6. The 3D NAND memory circuitry of claim 5 wherein each of the angles of said longitudinally-straight segments relative to the one straight major peripheral side of the memory array circuitry region is within 5° of 45°.

7. The 3D NAND memory circuitry of claim 1 wherein the memory array circuitry region non-linear edge and the adjacent circuitry region non-linear edge comprise respective longitudinally-straight segments that angle longitudinally with immediately longitudinally-adjacent of said longitudinally-straight segments along the one elongated major peripheral side of the memory array circuitry region, each of the longitudinal angles between said immediately longitudinally-adjacent of said longitudinally-straight segments being within 2.5° of 90° along the one elongated major peripheral side of the memory array circuitry region.

8. The 3D NAND memory circuitry of claim 7 wherein the one major peripheral side of the memory array circuitry region is straight, all of the longitudinally-straight segments angling relative to the one straight major peripheral side of the memory array circuitry region within 2.5° of 90° along the one straight major peripheral side of the memory array circuitry region.

9. The 3D NAND memory circuitry of claim 1 wherein the longitudinally non-linear edges form a longitudinal series of regions of material of the memory array circuitry region that project laterally into material of the adjacent circuitry region, individual of said projecting regions of memory array material being triangular in shape in a horizontal cross-section.

10. The 3D NAND memory circuitry of claim 1 wherein the longitudinally non-linear edges form a longitudinal series of regions of material of the memory array circuitry region that project laterally into material of the adjacent circuitry region a maximum distance “b” and that have an elevational thickness “h”, b:h being from 0.25 to 5.

11. The 3D NAND memory circuitry of claim 1 wherein the longitudinally non-linear edges form a longitudinal series of regions of material of the memory array circuitry region that project laterally into material of the adjacent circuitry region, that have a maximum width “a”, and that have an elevational thickness “h”; a:h being from 0.25 to 20.

12. The 3D NAND memory circuitry of claim 11 wherein the longitudinal series of regions of material of the memory array circuitry region that project laterally into material of the adjacent circuitry region do so a maximum distance “b”, b:h being from 0.25 to 5.

13. The 3D NAND memory circuitry of claim 1 wherein the memory array circuitry region comprises a via region proximate the one elongated major peripheral side of the memory array circuitry region and in which a plurality of conductive vias elevationally extend, the memory array circuitry region comprising a stack region comprising a stack of tiers of different materials that is immediately laterally adjacent to and contacting one elongated major peripheral side of the via region, the via region and the stack region having a respective longitudinally non-linear edge at an interface relative one another along the one elongated major peripheral side of the via region.

14. Three-D (3D) NAND memory circuitry, comprising:

a memory array circuitry region comprising a repeating array of elevationally extending strings of memory cells

an adjacent circuitry region immediately laterally adjacent to and contacting one elongated major peripheral side of the memory array circuitry region, the adjacent circuitry region being distinct in structure from the memory array circuitry region where contacting the memory array circuitry region and distinct in operation from the memory array circuitry region; and

the memory array circuitry region comprising a via region proximate the one elongated major peripheral side of the memory array circuitry region and in which a plurality of conductive vias elevationally extend, the memory array circuitry region comprising a stack region comprising a stack of tiers of different materials that is immediately laterally adjacent to and contacting one elongated major peripheral side of the via region, the via region and the stack region having a respective longitudinally non-linear edge at an interface relative one another along the one elongated major peripheral side of the via region.

15. The 3D NAND memory circuitry of claim 14 wherein the longitudinally non-linear edges form a longitudinal series of regions of material of the stack region that project laterally into material of the via region a maximum distance “d” and that have an elevational thickness “h”; d:h being from 0.05 to 1.0.

16. The 3D NAND memory circuitry of claim 14 wherein the longitudinally non-linear edges form a longitudinal series of regions of material of the stack region that project laterally into material of the via region, that have a maximum width “c”, and that have an elevational thickness “h”; c:h being from 0.1 to 4.0.

17. The 3D NAND memory circuitry of claim 14 wherein the longitudinally non-linear edges form a longitudinal series of regions of material of the stack region that project laterally into material of the via region, number of such laterally-projecting regions along the one elongated major peripheral side being no more than 3.

18. Three-D (3D) NAND memory circuitry, comprising:

a memory array circuitry region comprising a plurality of elevationally extending strings of memory cells and a periphery having a plurality of straight major peripheral sides;

a peripheral circuitry region surrounding and contacting each of the straight major peripheral sides of the periphery of the memory array circuitry region; and

the memory array circuitry region and the peripheral circuitry region having a respective longitudinally non-linear edge at an interface relative one another along individual of the straight major peripheral sides of the periphery of the memory array circuitry region circumferentially about the memory array circuitry region.

19. The 3D NAND memory circuitry of claim 18 wherein the memory array circuitry region comprises a plurality of spaced via regions proximate the memory array circuitry region periphery and individually in which a plurality of conductive vias elevationally extend, the memory array circuitry region comprising a stack region comprising a stack of tiers of different materials that is laterally adjacent to and contacts at least one straight major peripheral side of individual of the via regions, the individual via regions and the stack region having a respective longitudinally non-linear edge at respective interfaces relative one another along the one straight major peripheral side of the respective via regions.

20. The 3D NAND memory circuitry of claim 18 wherein the longitudinally non-linear edges form a longitudinal series of regions of material of the memory array circuitry region that project laterally into material of the peripheral circuit region, number of said projecting regions of material of the memory array circuitry region being no less than 1,000 along individual of the straight major peripheral sides.

21. The 3D NAND memory circuitry of claim 1 wherein the elevationally extending strings of memory cells are vertically extending strings of memory cells.

22. The 3D NAND memory circuitry of claim 1 wherein the elevationally extending strings of memory cells are arrayed in rectangular block segments.

23. The 3D NAND memory circuitry of claim 14 wherein the elevationally extending strings of memory cells are vertically extending strings of memory cells.

24. The 3D NAND memory circuitry of claim 14 wherein the elevationally extending strings of memory cells are arrayed in rectangular block segments.

25. The 3D NAND memory circuitry of claim 18 wherein the elevationally extending strings of memory cells are vertically extending strings of memory cells.

26. The 3D NAND memory circuitry of claim 18 wherein the elevationally extending strings of memory cells are arrayed in rectangular block segments.