Memory as a programmable logic device

1. A memory, comprising:

a data line;

a plurality of strings of series-connected memory cells selectively connected to the data line;

a plurality of first access lines, wherein each first access line of the plurality of first access lines is coupled to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells; and

a plurality of second access lines, wherein each second access line of the plurality of second access lines is coupled to a control gate of a respective memory cell of a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells;

wherein a particular second access line of the plurality of second access lines is coupled to the control gate of the respective memory cell of a particular string of series-connected memory cells of the plurality of strings of series-connected memory cells, and not coupled to a control gate of any memory cell of a different string of series-connected memory cells of the plurality of strings of series-connected memory cells.

2. A memory, comprising:

a data line;

a plurality of strings of series-connected memory cells selectively connected to the data line;

a plurality of first access lines, wherein each first access line of the plurality of first access lines is coupled to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells; and

a plurality of second access lines, wherein each second access line of the plurality of second access lines is coupled to a control gate of a respective memory cell of a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells;

wherein no second access line of the plurality of second access lines is coupled to a control gate of any memory cell of any string of series-connected memory cells of the plurality of strings of series-connected memory cells other than its respective string of series-connected memory cells of the plurality of strings of series-connected memory cells.

3. A method of operating a memory, comprising:

applying a plurality of first control signals concurrently to control gates of a first string of series-connected memory cells of the memory and to control gates of a second string of series-connected memory cells of the memory, wherein the plurality of first control signals comprises a plurality of pairs of complementary control signals, each pair of complementary control signals of the plurality of pairs of complementary control signals applied to a respective pair of control gates of the first string of series-connected memory cells and to a respective pair of control gates of the second string of series-connected memory cells;

applying a second control signal to a control gate of a particular memory cell of the first string of series-connected memory cells while applying the plurality of first control signals and without applying the second control signal to a control gate of any memory cell of the second string of series-connected memory cells; and

applying a third control signal to the control gate of a particular memory cell of the second string of series-connected memory cells while applying the plurality of first control signals and while applying the second control signal, and without applying the third control signal to the control gate of any memory cell of the first string of series-connected memory cells.

4. The method of claim 3 , further comprising:

applying the second control signal to a control gate of a particular memory cell of a third string of series-connected memory cells of the memory while applying the plurality of first control signals and while applying the second control signal to the control gate of the particular memory cell of the first string of series-connected memory cells.

5. The method of claim 3 , further comprising:

sensing a state of a data line connected to the first string of series-connected memory cells and connected to the second string of series-connected memory cells while applying the plurality of first control signals, the second control signal and the third control signal.

6. The method of claim 5 , wherein the first string of series-connected memory cells and the second string of series-connected memory cells are contained in a first block of memory cells of the memory, the method further comprising:

storing a result of the sensing of the state of the data line in a page buffer of the memory; and

reading the result of the sensing of the state of the data line from the page buffer into a shift register of the memory associated with a different block of memory cells of the memory.

7. The method of claim 6 , further comprising:

shifting the result from the shift register and applying it to a control gate of a memory cell of a string of series-connected memory cells of the different block of memory cells.

8. A method of operating a memory, comprising:

sensing a state of a first string of series-connected memory cells of the memory;

storing a result of the sensing of the state of the first string of series-connected memory cells in a page buffer of the memory;

reading the result of the sensing of the state of the first string of series-connected memory cells from the page buffer into a shift register of the memory;

selectively activating a particular memory cell of a second string of series-connected memory cells of the memory responsive to the result of the sensing of the state of the first string of series-connected memory cells in the shift register; and

applying a plurality of control signals to control gates of the second string of series-connected memory cells of the memory while selectively activating the particular memory cell of the second string of series-connected memory cells responsive to the result of the sensing of the state of the first string of series-connected memory cells in the shift register, wherein the plurality of control signals comprises a plurality of pairs of complementary control signals, each pair of complementary control signals of the plurality of pairs of complementary control signals applied to a respective pair of control gates of the second string of series-connected memory cells.

9. The method of claim 8 , further comprising:

sensing a state of the second string of series-connected memory cells while applying the plurality of control signals and while selectively activating the particular memory cell of the second string of series-connected memory cells responsive to the result of the sensing of the state of the first string of series-connected memory cells in the shift register.

10. The method of claim 8 , wherein the plurality of control signals is a first plurality of control signals, and wherein the sensing of the state of the first string of series-connected memory cells comprises:

applying a second plurality of control signals to control gates of the first string of series-connected memory cells, wherein the second plurality of control signals comprises a plurality of pairs of complementary control signals, each pair of complementary control signals of the plurality of pairs of complementary control signals applied to a respective pair of control gates of the first string of series-connected memory cells; and

sensing the state of the first string of series-connected memory cells while applying the second plurality of control signals.

11. The method of claim 8 , wherein the plurality of control signals is a first plurality of control signals, the method further comprising:

applying the first plurality of control signals to control gates of a third string of series-connected memory cells of the memory while selectively activating the particular memory cell responsive to the result of the sensing of the state of the first string of series-connected memory cells in the shift register; and

selectively activating a particular memory cell of the third string of series-connected memory cells responsive to a different result in the shift register.

12. The method of claim 8 , further comprising:

programming memory cells of the first string of series-connected memory cells such that pairs of complementary memory cells have complementary data states.