Monitoring and charging inhibit bit-line

1. A memory device, comprising:

a group of memory cells including a first memory cell coupled to a first bit line (BL) and a second memory cell coupled to a second BL; and

a BL charging circuit configured to provide an inhibit signal to the second BL in response to a control signal to program the first memory cell, wherein, to provide the inhibit signal, the BL charging circuit is configured to apply a supply voltage (V CC ) to the second BL for an initial wait time and, after the initial wait time, to apply a higher voltage than the supply voltage (V CC ) until the inhibit signal reaches a value of the supply voltage (V CC ).

2. The memory device of claim 1 , wherein the first memory cell includes a target memory cell to be programmed by a programming operation and the second memory cell includes a non-target memory cell to not be programmed by the programming operation, and wherein the first and second memory cells include NAND memory cells.

3. The memory device of claim 1 , wherein the BL charging circuit includes a first charging path coupled between the higher voltage and the second BL, and a second charging path coupled between the supply voltage (V CC ) and the second BL.

4. The memory device of claim 3 , where the first and second charging paths each include respective P-type metal-oxide-semiconductor (PMOS) transistors.

5. The memory device of claim 1 , wherein the initial wait time is a predetermined time period.

6. The memory device of claim 1 , wherein the higher voltage is a charge pump circuit or an external power supply.

7. The memory device of claim 1 , further comprising a BL voltage sensing circuit configured to sense a voltage on the second BL, and wherein the BL charging circuit is configured to switch from the supply voltage (V CC ) to the higher voltage to charge the second BL when the sensed voltage on the second BL exceeds a threshold voltage.

8. The memory device of claim 7 , wherein the BL charging circuit is configured to switch to the supply voltage (V CC ) to charge the second BL after the sensed voltage on the second BL reaches the value of the supply voltage (V CC ).

9. The memory device of claim 1 , comprising a memory control circuit configured to apply a voltage of substantially 0V to the first BL in response to the control signal to program the first memory cell.

10. The memory device of claim 9 , wherein the memory control circuit is configured to provide a programming signal to a word line (WL) coupled to the first memory cell.

11. The memory device of claim 10 , wherein the memory control circuit is configured to provide the programming signal to the WL when the inhibit signal on the second BL reaches a value of the supply voltage (V CC ).

12. The memory device of claim 11 , wherein the memory control circuit is configured to provide the programming signal to the WL further in response to a voltage on the first BL falling below a threshold.

13. A memory device, comprising:

an NAND memory cell array;

a memory control circuit coupled to the NAND memory cell array via a group of bit lines (BLs), including a first BL coupled to a string of NAND memory cells including a target memory cell to be programmed by a programming operation, and a second BL coupled to a string of NAND memory cells including a non-target memory cell to not be programmed by the programming operation, wherein the memory control circuit is configured to, in response to a control signal to program the first memory cell:

provide an inhibit signal to the second BL, wherein, to provide the inhibit signal, the memory control circuit is configured to apply a supply voltage (V CC ) to the second BL for an initial wait time and, after the initial wait time, apply a higher voltage than the supply voltage (V CC ) until the inhibit signal reaches a value of the supply voltage (V CC ); and

provide a programming signal to a word line (WL) coupled to the first memory cell when the inhibit signal on the second BL reaches a value of the supply voltage (V CC ).

14. A method of programming a memory device that includes a group of memory cells including a first memory cell coupled to a first bit line (BL) and a second memory cell coupled to a second BL, the method comprising:

in response to a control signal to program the first memory cell, providing an inhibit signal to the second BL by coupling a supply voltage (V CC ) to the second BL for an initial wait time; and

after the initial wait time, applying a higher voltage than the supply voltage (V CC ) to the second BL until the inhibit signal reaches a value of the supply voltage (V CC ).

15. The method of claim 14 , wherein the initial wait time is a predetermined time period.

16. The method of claim 14 , comprising:

sensing a voltage on the second BL; and

switching from the supply voltage (V CC ) to the higher voltage to charge the second BL when the sensed voltage on the second BL exceeds a threshold voltage.

17. The method of claim 16 , comprising switching to the supply voltage (V CC ) to charge the second BL after the sensed voltage on the second BL reaches the value of the supply voltage (V CC ).

18. The method of claim 14 , comprising applying a voltage of substantially 0V to the first BL in response to the control signal to program the first memory cell.

19. The method of claim 14 , comprising providing a programming signal to a word line (WL) coupled to the first memory cell when the inhibit signal on the second BL reaches a value of the supply voltage (V CC ).

20. The method of claim 19 , wherein providing a programming signal to the WL coupled to the first memory cell is further in response to a voltage of the first BL falling below a threshold.