Methods for fabricating 3D semiconductor device packages, resulting packages and systems incorporating such packages

1. A method for fabricating a semiconductor device package, the method comprising:

adhering a wafer comprising laterally spaced semiconductor die locations thereof to a carrier substrate with an active surface of the wafer facing the carrier substrate;

forming a dielectric material over a back side of the wafer;

placing a first level of singulated semiconductor dice in mutually laterally spaced relationship over respective semiconductor die locations;

connecting conductive pillars protruding from the back side of the wafer through the dielectric material to aligned terminal pads of the singulated semiconductor dice; and forming a dielectric material over back sides of the singulated semiconductor dice of the first level and into spaces therebetween.

2. The method of claim 1 , further comprising forming through vias through the dielectric material and into the back side of the wafer to active circuitry of the semiconductor die locations, lining the through vias with a dielectric material and filling the through vias with a conductive material to form the conductive pillars.

3. The method of claim 1 , further comprising, before adhering the wafer to the carrier substrate:

forming through vias in the wafer extending to an active circuitry of the semiconductor die locations;

lining the through vias with a dielectric material;

filling the through vias with a conductive material;

thinning the wafer from the back side thereof to expose the conductive material as the conductive pillars; and

after the wafer is adhered to the carrier substrate, forming the dielectric material over the back side of the wafer and leaving exposed ends of the conductive pillars.

4. The method of claim 1 , further comprising forming through vias through the dielectric material over the back sides of the singulated semiconductor dice of the first level and into the back sides thereof to active circuitry, lining the through vias in the semiconductor dice with a dielectric material and filling the through vias with conductive material to form the conductive pillars.

5. The method of claim 1 , further comprising, before placing the first level of singulated semiconductor dice in laterally spaced relationship over respective semiconductor die locations:

on at least one wafer, forming through vias in locations for the singulated semiconductor dice extending to active circuitry thereof;

lining the through vias with a dielectric material;

filling the through vias with conductive material; and

thinning the wafer from the back side thereof to expose the conductive material as conductive pillars.

6. The method of claim 1 , further comprising:

placing at least another level of singulated semiconductor dice in mutually laterally spaced relationship over respective singulated semiconductor dice of the first level to form die stacks; and

connecting conductive pillars protruding from the back sides of the first level of singulated semiconductor dice through the dielectric material to aligned terminal pads of the at least another level of singulated semiconductor dice.

7. The method of claim 6 , further comprising forming a dielectric material over back sides of the at least another level of singulated semiconductor dice and in spaces therebetween.

8. The method of claim 7 , further comprising making cuts of a first width between the die stacks and into scribe areas of singulated semiconductor dice of adjacent stacks and into, but not through, a material of the wafer comprising semiconductor die locations.

9. The method of claim 8 , further comprising forming an environmentally protective coating over a dielectric material on back sides of uppermost singulated semiconductor dice in each stack, over sides of the singulated semiconductor dice, and over sides of the material comprising the semiconductor die locations exposed by making the cuts.

10. The method of claim 9 , further comprising making second cuts narrower than and entirely within the first cuts into and through remaining material of the wafer comprising the semiconductor die locations and into an adhesive material adhering the wafer comprising the semiconductor die locations to the carrier substrate.

11. The method of claim 9 , wherein forming an environmentally protective coating comprises forming a silicon nitride or a silicon oxynitride coating.

12. The method of claim 1 , wherein connecting conductive pillars protruding from the back side of the wafer through the dielectric material to aligned terminal pads of the semiconductor dice comprises at least one of dielectric bonding of the singulated semiconductor dice to the semiconductor die locations or diffusion bonding of the conductive pillars to the respective terminal pads.

13. The method of claim 1 , wherein forming a dielectric material comprises forming a silicon oxide, a silicon nitride, a silicon oxynitride, a tetra ethyl orthosilicate (TEOS) oxide or an ozone/TEOS oxide.

14. A method of forming a semiconductor device package, the method comprising:

stacking multiple levels of singulated semiconductor dice in mutually laterally spaced relationship over respective semiconductor die locations on a back side of a wafer;

before stacking each singulated semiconductor die, forming a dielectric bond line material over a back side of a semiconductor die location or a back side of a lower level of singulated semiconductor die;

connecting terminal pads of singulated dice to respective conductive pillars exposed through the dielectric bond line material over the back sides of the semiconductor die locations or over the back sides of the lower level of singulated semiconductor dice;

making cuts of a first width into spaces between the singulated semiconductor dice, into a material in scribe areas thereof and into the material of the wafer within scribe areas between semiconductor die locations;

forming a coating over back sides of uppermost dice of the stacks, over sides of the singulated semiconductor dice and over the material of the wafer between semiconductor die locations; and

making cuts of a second, narrower width between the stacks into and through remaining material of the wafer between the semiconductor die locations.

15. The method of claim 14 , wherein forming a dielectric bond line material comprises forming a silicon oxide, a silicon nitride, a silicon oxynitride, a TEOS oxide or an O 3 /TEOS oxide.

16. The method of claim 14 , wherein forming a coating comprises forming a silicon nitride or a silicon oxynitride coating.

17. The method of claim 14 , wherein connecting comprises at least one of bonding with the dielectric bond line material or diffusion bonding of the conductive pillars to the respective terminal pads.

18. The method of claim 14 , wherein forming a dielectric bond line material comprises forming a dielectric material in situ.