Wiring with external terminal
View Patent ↗Apparatuses for providing external terminals of a semiconductor device are described. An example apparatus includes: a pad formation area including a plurality of pads disposed at an edge of the apparatus; a peripheral circuit area including a plurality of circuit blocks coupled to a memory cell array, each circuit block of the plurality of circuit blocks including a via disposed at a side opposite to the pad formation area with respect to each circuit block; and a plurality of conductors, each conductor coupling the via to the corresponding pad, and crossing over, at least in part, an area in the peripheral circuit area that is outside the circuit block comprising the via.
1. An apparatus comprising a semiconductor chip, wherein the semiconductor chip comprises:
an edge defining a termination of the semiconductor chip;
a pad formation area along the edge, the pad formation area comprising a plurality of pads arranged along the edge;
a via coupled to a corresponding one of the plurality of pads; and
a distribution conductor coupled between the via and the corresponding pad.
2. The apparatus of claim 1 , wherein the semiconductor chip further comprises one or more conductors in each of a first-level wiring layer and a second-level wiring layer.
3. The apparatus of claim 2 , wherein a distribution conductive layer of the distribution conductor is greater in thickness than each of any of the one or more conductors.
4. The apparatus of claim 2 , wherein a distribution conductive layer of the distribution conductor is at least five times as thick as each of any of the one or more conductors.
5. The apparatus of claim 1 , wherein the semiconductor chip further comprises a circuit block, and the circuit block comprises a first circuit and a transistor arranged between the first circuit and the via.
6. The apparatus of claim 5 , wherein the circuit block further comprises a second circuit associated with the first circuit and disposed in the pad formation area under at least one of the plurality of pads.
7. The apparatus of claim 1 , wherein the semiconductor chip further comprises at least a first-level wiring layer and a second-level wiring layer, the first-level wiring layer includes one or more first conductors and a first interlayer insulating film covering the one or more first conductors, and the second-level wiring layer includes one or more second conductors and a second interlayer insulating film covering the one or more second conductors.
8. The apparatus of claim 1 , wherein the semiconductor chip further comprises a circuit block comprising a first circuit, and
wherein the via is disposed along a first side of the first circuit that is opposite to a second side of the first circuit, and the pad formation area extends along the second side of the first circuit.
9. The apparatus of claim 1 , wherein the semiconductor chip further comprises:
a first-level wiring layer comprising a first metal layer; and
a second-level wiring layer between the first-level wiring layer and a distribution conductive layer of the distribution conductor, and
wherein the second-level wiring layer comprises a second metal layer.
10. The apparatus of claim 9 ; wherein the first metal layer is made of a low conductivity material and the second metal layer is made of a middle conductivity material.
11. A semiconductor chip, comprising:
a data queue (DQ) circuit comprising a via made of a metal layer;
a distribution conductive layer having a portion disposed on the metal layer; and
a pad disposed on a portion of the distribution conductive layer and in a pad formation area, the pad formation area positioned on an opposite side of the DQ circuit from the via.
12. The semiconductor chip of claim 11 , wherein the DQ circuit comprises a first circuit, and
wherein the via is disposed along a first side of the first circuit that is opposite to a second side of the first circuit, and the pad formation area extends along the second side of the first circuit.
13. The semiconductor chip of claim 12 , wherein the DQ circuit further comprises a second circuit associated with the first circuit and disposed in the pad formation area.
14. The semiconductor chip of claim 11 , further comprising:
first, second, third, and fourth-level wiring layers each comprising a corresponding metal layer and a corresponding interlayer insulating film.
15. The semiconductor chip of claim 11 , further comprising:
a first-level wiring layer and a second-level wiring layer each comprising one or more conductors.
16. The semiconductor chip of claim 15 , wherein the distribution conductive layer is at least five times as thick as each of any of the one or more conductors.
17. An apparatus comprising:
a pad formation area comprising a plurality of pads;
a peripheral circuit area comprising a via disposed at a side opposite to the pad formation area; and
a plurality of conductors comprising a conductor coupling the via to a corresponding one the plurality of pads, the conductor crossing over, at least in part, an area in the peripheral circuit area between the via and the corresponding pad.
18. The apparatus of claim 17 , further comprising:
first and second-level wiring layers each comprising one or more conductors,
wherein a conductive layer of the conductor coupling the via to the corresponding pad is at least five times as thick as each of any of the one or more conductors.
19. The apparatus of claim 18 , further comprising:
a semiconductor substrate that is at an opposite side to the second-level wiring layer with respect to the first-level wiring layer,
wherein the first and second-level wiring layers comprise first and second metal layers, respectively, and
wherein the via is made of the second metal layer.
20. The apparatus of claim 17 , further comprising:
a semiconductor substrate; and
a first circuit comprising at least one transistor made, at least in part, of the semiconductor substrate,
wherein the via is disposed along a first side of the first circuit.