Apparatus having memory arrays and having trim registers associated with memory array access operation commands

1. An apparatus, comprising:

an external controller;

a memory in communication with the external controller and storing trim settings corresponding to a plurality of modes of operation; and

a memory device in communication with the external controller, the memory device comprising:

an array of memory cells;

an internal controller; and

a trim register array comprising a plurality of trim registers;

wherein the internal controller is configured to load trim settings to a trim register of the trim register array in response to a command received from the external controller;

wherein the internal controller is further configured to set trims in response to the trim settings of the trim register in response to receiving an access command associated with the trim settings of the trim register; and

wherein the internal controller is further configured to perform an access operation on the array of memory cells using the trims in response to receiving the access command; and

wherein the external controller is configured, in response to receiving a command from an external device indicative of a desired mode of operation, to select trim settings corresponding to the desired mode of operation, and to transmit the selected trim settings to the memory device.

2. The apparatus of claim 1 , wherein the external controller is configured to generate a command to the memory device to load the selected trim settings to the trim register of the memory device, wherein the command to the memory device comprises the selected trim settings.

3. The apparatus of claim 1 , wherein the memory in communication with the external controller is internal to the external controller.

4. The apparatus of claim 1 , wherein the memory in communication with the external controller is external to the external controller.

5. The apparatus of claim 1 , wherein the internal controller is further configured to load the trim settings into the trim register while performing a prior access operation on the array of memory cells.

6. The apparatus of claim 1 , wherein the internal controller is further configured to associate the trim settings of the trim register with the access command.

7. The apparatus of claim 6 , wherein the internal controller is further configured to associate the trim settings of the trim register with the access command by loading trim settings to trim registers of the trim register array in sequence.

8. The apparatus of claim 1 , wherein the internal controller is further configured to load the trim settings to the trim register of the trim register array in response to a particular command received from the external controller that is different than the received access command.

9. The apparatus of claim 8 , wherein the particular command comprises a command code and a confirm code, and data between the command code and the confirm code corresponding to the trim settings for the trim register.

10. The apparatus of claim 8 , wherein the particular command is a command received by the internal controller immediately prior to the access command.

11. The apparatus of claim 1 , wherein the internal controller being configured to load the trim settings to the trim register of the trim register array in response to the command received from the external controller comprises the internal controller being configured to load respective trim settings to respective trim registers of the trim register array comprising an array of N trim registers in response to receiving N commands for access operations on the array of memory cells, wherein N is an integer value, wherein each of the N trim registers are associated with a corresponding one of the N commands for access operations on the array of memory cells cycling from a first trim register of the array of N trim registers for a first command of the N commands for access operation on the array of memory cells to an Nth register of the array of N trim registers for an Nth command of the N commands for access operations on the array of memory cells.

12. The apparatus of claim 11 , wherein the internal controller is further configured to load trim settings into the first trim register of the array of N trim registers in response to receiving a subsequent (N+1)th command for an access operation on the array of memory cells.

13. The apparatus of claim 1 , wherein the command received from the external controller is a first command received from the external controller, and wherein the trim register of the trim register array is a first trim register of the trim register array, the apparatus further comprising:

wherein the internal controller is further configured to load trim settings to a second trim register of the trim register array in response to a second command received from the external controller;

wherein the internal controller is further configured to set trims for a subsequent access operation on the array of memory cells in response to the trim settings of the second trim register in response to receiving a subsequent access command associated with the trim settings of the second trim register; and

wherein the internal controller is further configured to perform the subsequent access operation on the array of memory cells using the trims for the subsequent access operation in response to receiving the subsequent access command.

14. An apparatus, comprising:

an external controller;

a memory in communication with the external controller and storing trim settings corresponding to a plurality of modes of operation; and

a memory device in communication with the external controller, the memory device comprising:

an array of memory cells;

an internal controller; and

a trim register array comprising a plurality of trim registers;

wherein the internal controller is configured to load trim settings to a particular trim register of the trim register array in response to a command received from the external controller;

wherein the internal controller is further configured to transfer the trim settings from the particular trim register of the trim register array to a different register of the trim register array;

wherein the internal controller is further configured to set trims in response to the trim settings of the different trim register in response to receiving an access command associated with the trim settings of the different trim register; and

wherein the internal controller is further configured to perform an access operation on the array of memory cells using the trims in response to receiving the access command; and

wherein the external controller is configured, in response to receiving a command from an external device indicative of a desired mode of operation, to select trim settings corresponding to the desired mode of operation, and to transmit the selected trim settings to the memory device.

15. The apparatus of claim 14 , wherein the internal controller is further configured to load the trim settings to the particular trim register in response to a command for a first access operation on the array of memory cells, and to load second trim settings to the particular trim register, after transferring the trim settings from the particular trim register to the different register, and in response to a command for a subsequent access operation on the array of memory cells.

16. The apparatus of claim 14 , wherein the internal controller is further configured to transfer the trim settings from the particular trim register to the different register in response to completing the access operation on the array of memory cells.

17. The apparatus of claim 14 , wherein the internal controller is further configured to perform an access operation on the array of memory cells comprising an operation type selected from the group consisting of a read operation, a program operation and an erase operation.

18. An apparatus, comprising:

an external controller;

a memory in communication with the external controller and storing trim settings corresponding to a plurality of modes of operation; and

a memory device in communication with the external controller, the memory device comprising:

an array of memory cells;

an internal controller; and

a trim register array comprising a plurality of trim registers;

wherein the internal controller is configured to load trim settings to a particular trim register of the trim register array in response to a command for an access operation on the array of memory cells received from the external controller;

wherein the internal controller is further configured to set trims for the access operation in response to the trim settings of the particular trim register in response to receiving the command for the access operation associated with the trim settings of the particular trim register;

wherein the internal controller is further configured to perform the access operation on the array of memory cells using the trims for the access operation in response to receiving the command for the access operation;

wherein the internal controller is further configured to load trim settings to a different trim register of the trim register array in response to a command for a subsequent access operation on the array of memory cells received from the external controller;

wherein the internal controller is further configured to set trims for the subsequent access operation in response to the trim settings of the different trim register in response to receiving the command for the subsequent access operation associated with the trim settings of the different trim register; and

wherein the internal controller is further configured to perform the subsequent access operation on the array of memory cells using the trims for the subsequent access operation in response to receiving the command for the subsequent access operation; and

wherein the external controller is configured, in response to receiving a command from an external device indicative of a desired mode of operation, to select trim settings corresponding to the desired mode of operation, and to transmit the selected trim settings to the memory device.

19. The apparatus of claim 18 , wherein the selected trim settings comprise the trim settings to be loaded to the particular trim register and the trim settings to be loaded to the different trim register.

20. The apparatus of claim 18 , wherein the trim settings to be loaded to the particular trim register and the trim settings to be loaded to the different trim register each comprise a different set of trim settings.