IP Library Granted Patent US 9,997,246
Granted Patent B2
US 9,997,246 · App. 15/015,424 · Granted Jun 12, 2018

Memory devices and their operation having trim registers associated with access operation commands

Inventor: Terry Grunzke (Boise, ID)
Assignee: Micron Technology, Inc.
G11C16/0483G06F12/0246G11C7/1072G11C16/06G11C29/028G06F2212/7207G11C2029/4402
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Quick Facts
Patent No.
US 9,997,246
App. No.
15/015,424
Granted
Jun 12, 2018
Kind
B2
Abstract

Methods including performing an access operation on a memory device using trims corresponding to trim settings, receiving a command to suspend the access operation, loading updated trim settings into a particular trim register of the memory device, setting updated trims for the access operation in response to the updated trim settings of the particular trim register, and resuming the access operation using the updated trims. Apparatus including an external controller and a memory device having an internal controller configured to set trims in response to trim settings and to perform an access operation on an array of memory cells using the trims in response to receiving the access command, wherein the external controller is configured to select trim settings corresponding to a desired mode of operation, and to transmit the selected trim settings to the memory device.

Claims (60)

1. A method, comprising:

performing an access operation on a memory device using trims corresponding to trim settings;

receiving a command at the memory device to suspend the access operation;

after receiving the command to suspend the access operation, suspending the access operation;

after suspending the access operation, receiving a command at the memory device to load updated trim settings, wherein the command to load the updated trim settings is associated with the updated trim settings to be received by the memory device;

after receiving the command to load the updated trim settings and receiving the updated trim settings, loading the updated trim settings into a particular trim register of the memory device;

setting updated trims for the access operation in response to the updated trim settings in the particular trim register; and

resuming the suspended access operation using the updated trims.

2. The method of claim 1 , further comprising:

receiving a command at the memory device for the access operation; and

setting the trims in response to the trim settings prior to performing the access operation.

3. The method of claim 2 , further comprising loading a trim register with the trim settings prior to setting the trims.

4. The method of claim 3 , further comprising loading the trim register with the trim settings in response to receiving the command for the access operation.

5. The method of claim 1 , wherein resuming the suspended access operation comprises resuming the suspended access operation in response to receiving a command at the memory device to resume the suspended access operation.

6. The method of claim 1 , wherein resuming the suspended access operation comprises resuming the suspended access operation in response to completion of an operation initiated after receiving the command to suspend the access operation.

7. A method, comprising:

receiving a command at a memory device to perform an access operation on a grouping of memory cells of an array of memory cells of the memory device;

setting trims in response to trim settings;

performing the access operation on the grouping of memory cells using the trims;

receiving a command at the memory device to suspend the access operation; after receiving the command to suspend the access operation, suspending the access operation;

after suspending the access operation, receiving a command at the memory device to load updated trim settings, wherein the command to load the updated trim settings is associated with the updated trim settings to be received by the memory device;

after receiving the command to load the updated trim settings and receiving the updated trim settings, loading the updated trim settings into a particular trim register of the memory device;

setting updated trims for the access operation in response to the updated trim settings in the particular trim register; and

resuming the suspended access operation using the updated trims in response to a criteria selected from a group consisting of receiving a command to resume the suspended access operation, and completion of an intervening access operation performed while the access operation is suspended.

8. The method of claim 7 , further comprising storing the trim settings to the particular trim register prior to loading the updated trim settings into the particular trim register.

9. The method of claim 8 , further comprising loading the updated trim settings into the particular trim register in response to the command to load the updated trim settings, wherein the command to load the updated trim settings is a different command received by the memory device than the command to suspend the access operation.

10. The method of claim 7 , further comprising:

receiving a subsequent command to perform the intervening operation on a different grouping of memory cells of the array of memory cells while the access operation is suspended; and

performing the intervening operation on the different grouping of memory cells.

11. A method, comprising:

receiving a command to perform an access operation on a grouping of memory cells of an array of memory cells of a memory device;

setting trims in response to trim settings;

performing the access operation on the grouping of memory cells using the trims;

receiving a command to suspend the access operation;

loading updated trim settings into a particular trim register of the memory device in response to the command to suspend the access operation;

setting updated trims for the access operation in response to the updated trim settings of the particular trim register; and

resuming the access operation using the updated trims in response to a criteria selected from a group consisting of receiving a command to resume the suspended access operation, and completion of an intervening operation performed while the access operation is suspended.

12. The method of claim 11 , wherein setting the trims in response to the trim settings comprises setting parameters to be utilized by the memory device to perform the access operation on the grouping of memory cells in response to the trim settings.

13. The method of claim 12 , wherein setting parameters to be utilized by the memory device to perform the access operation comprises setting at least one parameter selected from a group consisting of voltages to be applied during the access operation, voltage differentials to be utilized during the access operation, and quantities to be utilized during the access operation.

14. The method of claim 11 , wherein setting the updated trims for the access operation is further in response to the selected criteria for resuming the suspended access operation.

15. A method, comprising:

performing an access operation on a memory device using trims corresponding to trim settings;

receiving a command to suspend the access operation;

storing the trim settings to a particular trim register of the memory device in response to receiving the command to suspend the access operation;

loading updated trim settings into the particular trim register;

setting updated trims for the access operation in response to the updated trim settings in the particular trim register; and

resuming the access operation using the updated trims.

16. The method of claim 11 , further comprising:

loading a trim register associated with the command to perform the access operation with the trim settings while the memory device is performing a prior access operation on a different grouping of memory cells of the array of memory cells.

17. A method, comprising:

receiving a command to perform a particular access operation on a grouping of memory cells of an array of memory cells of a memory device;

setting trims in response to trim settings;

performing the particular access operation on the grouping of memory cells using the trims;

receiving a command to suspend the particular access operation;

after receiving the command to suspend the particular access operation, suspending the particular access operation, after suspending the particular access operation, receiving updated trim settings from a device external to the memory device, and loading the updated trim settings into a particular trim register of the memory device;

setting updated trims for the particular access operation in response to the updated trim settings in the particular trim register;

resuming the suspended particular access operation using the updated trims in response to a criteria selected from a group consisting of receiving a command to resume the suspended particular access operation, and completion of an intervening access operation performed while the particular access operation is suspended; and

storing the trim settings into the particular trim register prior to loading the updated trim settings into the particular trim register when the selected criteria is the completion of the intervening access operation performed while the particular access operation is suspended.

18. The method of claim 17 , wherein, when the selected criteria is the receiving of the command to resume the suspended particular access operation, resuming the suspended particular access operation comprises resuming the suspended particular access operation in response to receiving the command to resume the suspended particular access operation.

19. The method of claim 17 , wherein setting the trims in response to the trim settings comprises setting parameters to be utilized by the memory device to perform the access operation on the grouping of memory cells in response to the trim settings, the parameters selected from a group consisting of voltages to be applied during the particular access operation, voltage differentials to be utilized during the particular access operation, and quantities to be utilized during the particular access operation.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
Continuity (2)
Division 13723781 · Dec 21, 2012
Related Publication 20160155507A1 · Jun 2, 2016