IP Library Granted Patent US 10,553,595
Granted Patent B2
US 10,553,595 · App. 16/007,054 · Granted Feb 4, 2020

Memory cell and an array of memory cells

Inventors: Durai Vishak Nirmal Ramaswamy (Boise, ID); Wayne Kinney (Emmett, ID); Marco Domenico Tiburzi (Avezzano, IT)
Assignee: Micron Technology, Inc.
H01L27/11507H01L27/11514G11C11/21G11C11/24
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Quick Facts
Patent No.
US 10,553,595
App. No.
16/007,054
Granted
Feb 4, 2020
Kind
B2
Abstract

A memory cell includes a first electrode and a second electrode. A select device and a programmable device are in series with each other between the first and second electrodes. The select device is proximate and electrically coupled to the first electrode. The programmable device is proximate and electrically coupled to the second electrode. The programmable device includes a radially inner electrode having radially outer sidewalls. Ferroelectric material is radially outward of the outer sidewalls of the inner electrode. A radially outer electrode is radially outward of the ferroelectric material. One of the outer electrode or the inner electrode is electrically coupled to the select device. The other of the outer electrode and the inner electrode is electrically coupled to the second electrode. Arrays of memory cells are disclosed.

Claims (31)

1. A memory cell, comprising:

a first electrode and a second electrode;

a select device and a programmable device in series with each other between the first and second electrodes, the select device being proximate and electrically coupled to the first electrode, the programmable device being proximate and electrically coupled to the second electrode; and

the programmable device comprising:

a radially inner electrode having radially outer sidewalls;

ferroelectric material, all of the ferroelectric material that is in all of the programmable device being radially outward of the radially outer sidewalls of the radially inner electrode;

a radially outer electrode radially outward of the ferroelectric material; and

one of the radially outer electrode or the radially inner electrode being electrically coupled to the select device, the other of the radially outer electrode and the radially inner electrode being electrically coupled to the second electrode, the ferroelectric material and the radially inner electrode having elevationally coincident elevationally outermost surfaces.

2. The memory cell of claim 1 wherein the elevationally coincident elevationally outermost surfaces of the ferroelectric material and the radially inner electrode are horizontally planar.

3. The memory cell of claim 1 wherein the first electrode comprises one horizontally elongated line and the second electrode comprises another horizontally elongated line.

4. The memory cell of claim 1 wherein the radially inner electrode overall is wider at its top than at its bottom.

5. The memory cell of claim 1 wherein the radially outer electrode overall is wider at its top than at its bottom.

6. The memory cell of claim 1 wherein the ferroelectric material overall is wider at its top than at its bottom.

7. The memory cell of claim 1 wherein,

the radially inner electrode overall is wider at its top than at its bottom;

the radially outer electrode overall is wider at its top than at its bottom; and

the ferroelectric material overall is wider at its top than at its bottom.

8. A memory cell, comprising:

a first upper electrode and a second lower electrode;

a select device and a programmable device in series with each other between the first and second electrodes, the select device being directly electrically coupled to the first upper electrode, the programmable device being directly electrically coupled to the second lower electrode; and

the programmable device comprising:

a radially inner electrode having radially outer sidewalls;

ferroelectric material, all of the ferroelectric material that is in all of the programmable device being radially outward of the radially outer sidewalls of the radially inner electrode; and

a radially outer electrode radially outward of the ferroelectric material.

9. The memory cell of claim 8 wherein the radially inner electrode overall is wider at its top than at its bottom.

10. The memory cell of claim 8 wherein the radially outer electrode overall is wider at its top than at its bottom.

11. The memory cell of claim 8 wherein the ferroelectric material overall is wider at its top than at its bottom.

12. The memory cell of claim 8 wherein,

the radially inner electrode overall is wider at its top than at its bottom;

the radially outer electrode overall is wider at its top than at its bottom; and

the ferroelectric material overall is wider at its top than at its bottom.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 11, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050713/0001 →
SUPPLEMENT NO. 9 TO PATENT SECURITY AGREEMENT Recorded Aug 9, 2018
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 047282/0463 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
Continuity (3)
Continuation 15275895 · Sep 26, 2016
Continuation 14305459 · Jun 16, 2014
Related Publication 20180294271A1 · Oct 11, 2018