IP Library Granted Patent US 10,074,662
Granted Patent B2
US 10,074,662 · App. 15/275,895 · Granted Sep 11, 2018

Memory cell and an array of memory cells

Inventors: Durai Vishak Nirmal Ramaswamy (Boise, ID); Wayne Kinney (Emmett, ID); Marco Domenico Tiburzi (Avezzano, IT)
Assignee: Micron Technology, Inc.
H01L27/11507H01L27/11514
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Quick Facts
Patent No.
US 10,074,662
App. No.
15/275,895
Granted
Sep 11, 2018
Kind
B2
Abstract

A memory cell includes a first electrode and a second electrode. A select device and a programmable device are in series with each other between the first and second electrodes. The select device is proximate and electrically coupled to the first electrode. The programmable device is proximate and electrically coupled to the second electrode. The programmable device includes a radially inner electrode having radially outer sidewalls. Ferroelectric material is radially outward of the outer sidewalls of the inner electrode. A radially outer electrode is radially outward of the ferroelectric material. One of the outer electrode or the inner electrode is electrically coupled to the select device. The other of the outer electrode and the inner electrode is electrically coupled to the second electrode. Arrays of memory cells are disclosed.

Claims (33)

1. A memory cell, comprising:

a first upper electrode and a second lower electrode;

a select device and a programmable device in series with each other between the first and second electrodes, the select device being directly electrically coupled to the first upper electrode, the programmable device being directly electrically coupled to the second lower electrode;

the programmable device comprising:

a radially inner electrode having radially outer sidewalls;

ferroelectric material radially outward of the radially outer sidewalls of the radially inner electrode; and

a radially outer electrode radially outward of the ferroelectric material; and

further comprising dielectric material elevationally between and directly against the select device and the radially inner electrode, the dielectric material being directly against radially internal sidewalls of the radially outer electrode.

2. A memory cell, comprising:

a first upper electrode and a second lower electrode;

a select device and a programmable device in series with each other between the first and second electrodes, the select device being directly electrically coupled to the first upper electrode, the programmable device being directly electrically coupled to the second lower electrode;

the programmable device comprising:

a radially inner electrode having radially outer sidewalls;

ferroelectric material radially outward of the radially outer sidewalls of the radially inner electrode; and

a radially outer electrode radially outward of the ferroelectric material; and

further comprising dielectric material elevationally between and directly against the select device and the ferroelectric material, the dielectric material being directly against radially internal sidewalls of the radially outer electrode.

3. The memory cell of claim 2 wherein the dielectric material is also elevationally between and directly against the select device and the radially inner electrode.

4. A memory cell, comprising:

a first upper electrode and a second lower electrode;

a select device and a programmable device in series with each other between the first and second electrodes, the select device being directly electrically coupled to the first upper electrode, the programmable device being directly electrically coupled to the second lower electrode; and

the programmable device comprising:

a radially inner electrode having radially outer sidewalls and having an upwardly open cylinder-like shape in a vertical cross section taken through an axial center of the radially inner electrode;

ferroelectric material radially outward of the radially outer sidewalls of the radially inner electrode;

a radially outer electrode radially outward of the ferroelectric material; and

dielectric material radially within the upwardly open cylinder-like shape of the radially inner electrode and which is directly against the select device.

5. A memory cell, comprising:

a first upper electrode and a second lower electrode;

a select device and a programmable device in series with each other between the first and second electrodes, the select device being directly electrically coupled to the first upper electrode, the programmable device being directly electrically coupled to the second lower electrode; and

the programmable device comprising:

a radially inner electrode having radially outer sidewalls and having an upwardly open cylinder-like shape in a vertical cross section taken through an axial center of the radially inner electrode;

ferroelectric material radially outward of the radially outer sidewalls of the radially inner electrode;

a radially outer electrode radially outward of the ferroelectric material; and

the ferroelectric material and the radially inner electrode having elevationally coincident elevationally outermost surfaces.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050680/0268 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 2 TO PATENT SECURITY AGREEMENT Recorded Feb 10, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041671/0902 →
Continuity (2)
Continuation 14305459 · Jun 16, 2014
Related Publication 20170033115A1 · Feb 2, 2017