Patent Assignment
Reel/Frame 041671/0902
Supplement No. 2 to Patent Security Agreement
Recorded: 2017-02-10
Pages: 16
Assignor
MICRON TECHNOLOGY, INC.
Executed: 2016-10-24
Assignee
MORGAN STANLEY SENIOR FUNDING, INC.
1300 THAMES STREET, 4TH FLOOR, BALTIMORE, MARYLAND, 21231
Covered Properties
(181)
System and Method for Controlling User Access to an Electronic Device
Program and Read Trim Setting
Systems and Methods for Providing File Information in a Memory System Protocol
Light Emitting Devices with Built-in Chromaticity Conversion and Methods of Manufacturing
Methods of Forming Capacitors
External Gettering Method and Device
Methods of Forming Diodes
Apparatuses and Methods for Providing Reference Voltages
Apparatus and Methods Including Source Gates
Ferroelectric Memory Cell Recovery
Patent:
9,697,913 →
Application:
15/179,695 →
Three Dimensional Memory and Methods of Forming the Same
Writing to Cross-Point Non-Volatile Memory
Patent:
9,613,676 →
Application:
15/197,416 →
Error Correction Code Event Detection
Textured Devices
Devices, Systems, and Methods to Synchronize Simultaneous Dma Parallel Processing of a Single Data Stream by Multiple Devices
Memory Device with Reduced Neighbor Memory Cell Disturbance
Devices, Systems, and Methods of Reducing Chip Select
Space Efficient Random Decision Forest Models Implementation Utilizing Automata Processors
Select Device for Memory Cell Applications
Memory Device Including Concurrent Suspend States for Different Operations
Apparatuses and Methods for Storing a Data Value in a Sensing Circuitry Element
Patent:
9,767,864 →
Application:
15/216,256 →
Shifting Data in Sensing Circuitry
Adaptive routing to avoid non-repairable memory and logic defects on automata processor
Apparatuses and Methods for Reducing Off State Leakage Currents
Shared Error Detection and Correction Memory
Array Of Conductive Vias, Methods Of Forming A Memory Array, And Methods Of Forming Conductive Vias
Electromagnetic Shield and Associated Methods
Accessing Status Information
Semiconductor Device Including Buffer Circuit
Methods and Apparatuses Having Memory Cells Including a Monolithic Semiconductor Channel
Method and Apparatus for Inductive Coupling Signal Transmission
Apparatuses and Methods for Integrated Interleaved Reed-Solomon Encoding and Decoding
Apparatuses and Methods for Interleaved Bch Codes
Semiconductor Constructions and NAND Unit Cells
Apparatuses and Methods for Operations in a Self-Refresh State
Textured Memory Cell Structures
Variable Page Size Architecture
Stacked Semiconductor Die Assemblies with Die Support Members and Associated Systems and Methods
Interconnection Systems
Interrupted Write Operation in a Serial Interface Memory with a Portion of a Memory Address
Power Management
Hybrid Memory Drives, Computer System, and Related Method for Operating a Multi-Mode Hybrid Drive
Solid-State Radiation Transducer Devices Having at Least Partially Transparent Buried-Contact Elements, and Associated Systems and Methods
Apparatuses and Methods for Random Number Generation
Apparatuses and Methods Using Dummy Cells Programmed to Different States
Proactive Corrective Actions in Memory Based on a Probabilistic Data Structure
Vertical String Of Memory Cells Individually Comprising A Programmable Charge Storage Transistor Comprising A Control Gate And A Charge storage Structure And Method Of Forming A Vertical String Of Memory Cells Individually Comprising A Programmable Charge Storage Transistor Comprising A Control Gate And A Charge Storage Structure
Interconnect Structure with Improved Conductive Properties and Associated Systems and Methods
Stacked Semiconductor Die Assemblies with Support Members and Associated Systems and Methods
Package-On-Package Semiconductor Assemblies and Methods of Manufacturing the Same
Semiconductor Device Including Semiconductor Chips Mounted Over Both Surfaces of Substrate
Multi-Deck Memory Device with Access Line and Data Line Segregation Between Decks and Method of Operation Thereof
Determining Soft Data from a Hard Read
Apparatuses Including Multi-Level Memory Cells and Methods of Operation of Same
Methods of Forming an Array of Elevationally-Extending Strings of Memory Cells Comprising a Programmable Charge Storage Transistor and Arrays of Elevationally-Extending Strings of Memory Cells Comprising a Programmable Charge Storage Transistor
Semiconductor Devices and Packages Including Conductive Underfill Material and Related Methods
Application:
15/232,525 →
Publication:
US 2016/0351530
Functional Data Reading in a Non-Volatile Memory
Connections for Memory Electrode Lines
Semiconductor Layered Device with Data Bus
Methods of Forming Silicon Nitride by Atomic Layer Deposition and Methods of Forming Semiconductor Structures
Patent:
9,865,456 →
Application:
15/235,365 →
Semiconductor Device Suppressing Bti Deterioration
Smallest or Largest Value Element Determination
Multi-Function Resistance Change Memory Cells and Apparatuses Including the Same
Cross-Point Memory Cells, Non-Volatile Memory Arrays, Methods of Reading a Memory Cell, Methods of Programming a Memory Cell, Methods of Writing to and Reading from a Memory Cell, and Computer Systems
Methods of Forming Magnetic Memory Cells and Semiconductor Devices
Methods of Operating Memory
Methods of Operating Ferroelectric Memory Cells, and Related Ferroelectric Memory Cells and Capacitors
Segmented Memory and Operation
Patent:
9,773,553 →
Application:
15/241,740 →
Method, Apparatus, and System Providing an Imager with Pixels Having Extended Dynamic Range
Apparatuses and Methods for Adjusting Delay of Command Signal Path
Sequential Memory Access Operations
Threshold Voltage Analysis
Semiconductor Structures Including Liners Comprising Alucone and Related Methods
Apparatus and Method for Instant-on Quadra-Phase Signal Generator
Temperature-Dependent Refresh Circuit Configured to Increase or Decrease a Count Value of a Refresh Timer According to a Self-Refresh Signal
Timing Control Circuit Shared by a Plurality of Banks
Apparatus and Methods Related to Microcode Instructions Indicating Instruction Types
Full Bias Sensing in a Memory Array
Command Queuing
Methods of Forming Memory Arrays
Apparatuses and Methods for Encoding Using Error Protection Codes
Programming Methods and Memories
Temperature Compensation in Memory Sensing
Integrated Structures and Methods of Forming Vertically-Stacked Memory Cells
Light-Emitting Metal-Oxide-Semiconductor Devices and Associated Systems, Devices, and Methods
Systems and Methods Using Single Antenna for Multiple Resonant Frequency Ranges
Data Shifting
Apparatuses for Reducing Clock Path Power Consumption in Low Power Dynamic Random Access Memory
Methods of Forming Magnetic Memory Cells, and Methods of Forming Arrays of Magnetic Memory Cells
Systems, Methods, and Apparatuses for Temperature and Process Corner Sensitive Control of Power Gated Domains
Apparatuses and/or Methods for Operating a Memory Cell as an Anti-Fuse
Hybrid Memory Device Using Different Types of Capacitors
Methods of Forming Semiconductor Device Structures Including Two-Dimensional Material Structures
Memory Devices for Pattern Matching
Vertical Light Emitting Devices with Nickel Silicide Bonding and Methods of Manufacturing
Stacked Semiconductor Die Assemblies with High Efficiency Thermal Paths and Associated Methods
Elevated Pocket Pixels, Imaging Devices and Systems Including the Same and Method of Forming the Same
Multiple Data Channel Memory Module Architecture
Vertical Memory Cell String with Dielectric in a Portion of the Body
Methods and Apparatuses Having Strings of Memory Cells Including a Metal Source
Apparatuses and Methods for Performing an Exclusive or Operation Using Sensing Circuitry
Methods and Apparatuses for Providing Data Received by a Plurality of State Machine Engines
Sense Circuits, Semiconductor Devices, and Related Methods for Resistance Variable Memory
Redundancy Array Column Decoder for Memory
Patent:
9,779,796 →
Application:
15/258,852 →
Semiconductor Memory Column Decoder Device and Method
Performing Logical Operations Using Sensing Circuitry
Methods and Systems for Data Analysis in a State Machine
Memory Device Configuration Commands
Apparatuses and Methods for Flexible Fuse Transmission
Patent:
9,666,307 →
Application:
15/265,671 →
System and Method for Decoding Commands Based on Command Signals and Operating State
Updating a Register in Memory
Determining Soft Data
Compensation for Threshold Voltage Variation of Memory Cell Components
Patent:
9,786,345 →
Application:
15/267,807 →
Storing Memory Array Operational Information in Nonvolatile Subarrays
Apparatuses and Methods for Generating Probabilistic Information with Current Integration Sensing
Apparatuses and Methods for Staircase Code Encoding and Decoding for Storage Devices
Solid State Transducer Dies Having Reflective Features Over Contacts and Associated Systems and Methods
Memory Devices and Electronic Systems Having a Hybrid Cache Including Static and Dynamic Caches with Single and Multiple Bits Per Cell, and Related Methods
Apparatuses and Methods for Performing Logical Operations Using Sensing Circuitry
Apparatus of Offset Voltage Adjustment in Input Buffer
Patent:
9,792,964 →
Application:
15/270,996 →
Methods of Forming a Semiconductor Device Structure Including a Stair Step Structure
Semiconductor Structures Including Carrier Wafers and Attached Device Wafers, and Methods of Forming Such Semiconductor Structures
Memory Cell And An Array Of Memory Cells
Dynamic Reference Voltage Determination
Patent:
9,847,117 →
Application:
15/276,139 →
Apparatuses and Methods for Semiconductor Circuit Layout
Systems and Methods for Forming Apertures in Microfeature Workpieces
3D Vertical Nand Memory Device Including Multiple Select Lines and Control Lines Having Different Vertical Spacing
Memory Arrays Having Confined Phase Change Material Structures Laterally Surrounded with Silicon Nitride.
Via Formation for Cross-Point Memory
Apparatuses and Methods for Segmented Sgs Lines
Validation of a Symbol Response Memory
Apparatuses and Methods to Change Data Category Values
System and Method for Individual Addressing
Semiconductor Device
Techniques for Sensing Logic Values Stored in Memory Cells Using Sense Amplifiers That Are Selectively Isolated from Digit Lines
Patent:
9,886,991 →
Application:
15/282,029 →
Method and Apparatus for a Volume Management System in a Non-Volatile Memory Device
Systems and Apparatuses for a Configurable Temperature Dependent Reference Voltage Generator
Thyristor Random Access Memory Device and Method
Interfaces and Die Packages, and Appartuses Including the Same
Generation and Application of Gray Codes
Patent:
9,697,892 →
Application:
15/284,666 →
Methods and Systems for Creating Networks
Methods and Systems for Event Reporting
Reprogrammable Non-Volatile Ferroelectric Latch for Use with a Memory Controller
Patent:
9,858,979 →
Application:
15/286,259 →
Methods and Systems for Representing Processing Resources
Shifting Data in Sensing Circuitry
Semiconductor Constructions and Memory Arrays
Two-Part Programming Methods
Apparatuses and Methods for Performing Compare Operations Using Sensing Circuitry
Concurrently Reading First and Second Pages of Memory Cells Having Different Page Addresses
Memory Having Internal Processors and Data Communication Methods in Memory
Apparatuses Including Stair-Step Structures and Methods of Forming the Same
Configuration Update for a Memory Device Based on a Temperature of the Memory Device
Semiconductor Devices Comprising Magnetic Memory Cells and Methods of Fabrication
A System for Handling Semiconductor Dies
Electronic Device Structures and Methods of Making
Compensating for Variations in Selector Threshold Voltages
Apparatuses and Methods to Perform Logical Operations Using Sensing Circuitry
Elevationally-Extending Strings Of Memory Cells Individually Comprising A Programmable Charge Storage Transistor And Methods Of Processing Silicon Nitride-Comprising Materials
Patent:
9,893,083 →
Application:
15/293,133 →
Circuit and Layout for Single Gate Type Precharge Circuit for Data Lines in Memory Device
Systems and Methods to Determine Motion Parameters Using Rfid Tags
Methods of Forming an Array of Elevationally-Extending Strings of Memory Cells, Methods of Forming Polysilicon, Elevationally-Extending Strings of Memory Cells Individually Comprising a Programmable Charge Storage Transistor, and Electronic Components Comprising Po
Apparatuses and Methods for an Operating System Cache in a Solid State Device
Devices Comprising A Capacitor And Support Material That Laterally Supports The Capacitor
Semiconductor Devices and Methods of Fabrication
Memory Including a Selector Switch on a Variable Resistance Memory Cell
Apparatuses and Methods to Selectively Perform Logical Operations
Patent:
9,805,772 →
Application:
15/298,798 →
Semiconductor Devices Including Back-Side Integrated Circuitry
Apparatuses and Methods for Phase Interpolating Clock Signals and for Providing Duty Cycle Corrected Clock Signals
Package-On-Package Semiconductor Device Assemblies Including One or More Windows and Related Methods and Packages
Application:
62/356,929 →
Memory Cells and Memory Arrays
Application:
62/381,685 →
Memory Cells and Memory Arrays
Application:
62/381,704 →
Memory Cells and Memory Arrays
Application:
62/381,720 →
Memory Cells and Memory Arrays
Application:
62/381,736 →
Memory Cells, Methods Of Forming An Array Of Two Transistor-One Capacitor Memory Cells, And Methods Used In Fabricating Integrated Circuitry
Application:
62/381,737 →
Sense Amplifier Constructions
Application:
62/381,745 →
Memory Arrays
Application:
62/381,753 →
Apparatuses and Methods Including Two Transistor-One Capacitor Memory and for Accessing Same
Application:
62/381,844 →
Apparatuses and Methods Including Ferroelectric Memory and for Operating Ferroelectric Memory
Application:
62/381,879 →
Apparatuses and Methods Including Ferroelectric Memory and for Accessing Ferroelectric Memory
Application:
62/381,900 →
Ferroelectric Memory Cells
Application:
62/381,942 →
Custom Compute Cores in Integrated Circuit Devices
Application:
62/410,732 →
Related Assignments
(10)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Sep 21, 2015
From: CARACCIO, DANILO; MIRICHIGNI, GRAZIANO; SANTOPIETRO, GIANFRANCO; FERRANTE, GIANFRANCO
To: MICRON TECHNOLOGY, INC.
Reel/Frame 036615/0131 →
Assignment of Assignor's Interest
Jul 20, 2016
From: FU, YAO; GLENDENNING, PAUL; TRACY, TOMMY, II; JONAS, ERIC
To: MICRON TECHNOLOGY, INC.
Reel/Frame 039199/0568 →
Corrective Assignment to Correct the Application Serial Number from 15214818 to 15214188 Previously Recorded on Reel 039199 Frame 0568. Assignor(S) Hereby Confirms the Assignment..
Jul 26, 2016
From: FU, YAO; GLENDENNING, PAUL; TRACY, TOMMY, II; JONAS, ERIC
To: MICRON TECHNOLOGY, INC.
Reel/Frame 039474/0367 →
Assignment of Assignor's Interest
Aug 9, 2016
From: WU, JUN; PAN, DONG
To: MICRON TECHNOLOGY, INC.
Reel/Frame 039387/0658 →
Assignment of Assignor's Interest
Oct 17, 2016
From: ZHANG, YIHUA; MANGALINDAN, PAOLO E.; LEI, JIANFEI; PROESCHOLDT, ANDREW D.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 040034/0776 →
Assignment of Assignor's Interest
Oct 17, 2016
From: WANG, BEI; CALDERONI, ALESSANDRO; KINNEY, WAYNE; JOHNSON, ADAM
To: MICRON TECHNOLOGY, INC.
Reel/Frame 040034/0878 →
Assignment of Assignor's Interest
Apr 14, 2017
From: MARIANI, MARCELLO; SERVALLI, GIORGIO; LOCATELLI, ANDREA
To: MICRON TECHNOLOGY, INC.
Reel/Frame 042015/0837 →
Security Interest
Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
Release of Security Interest
Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050680/0268 →
Release of Security Interest
Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →