Multi-deck memory device with access line and data line segregation between decks and method of operation thereof

1. An apparatus comprising:

a substrate;

a first memory cell block including first memory cell strings located over the substrate, and first data lines coupled to the first memory cell strings;

a second memory cell block including second memory cell strings located over the first memory cell block, the first memory block being physically located between the second memory block and the substrate, and second data lines coupled to the second memory cell strings, the first data lines being physically located between the second memory block and the substrate;

first conductive paths located over the substrate and coupled between the first data lines and buffer circuitry of the apparatus;

second conductive paths located over the substrate and coupled between the second data lines and the buffer circuitry, wherein no conductive path of the first and second conductive paths is shared by the first and second memory cell blocks;

access lines coupled to the first and second memory cell strings, wherein the first and second memory cell blocks share the access lines; and

transistors, each of the transistors coupled to a respective access line of the access lines, wherein the transistors include a common gate.

2. An apparatus comprising:

a substrate;

a first memory cell block including first memory cell strings located over the substrate, and first data lines coupled to the first memory cell strings;

a second memory cell block including second memory cell strings located over the first memory cell block, the first memory block being physically located between the second memory block and the substrate, and second data lines coupled to the second memory cell strings, the first data lines being physically located between the second memory block and the substrate;

first conductive paths located over the substrate and coupled between the first data lines and buffer circuitry of the apparatus; and

second conductive paths located over the substrate and coupled between the second data lines and the buffer circuitry, wherein no conductive path of the first and second conductive paths is shared by the first and second memory cell blocks, wherein the buffer circuitry includes:

a first buffer circuit;

a first transistor coupled between the first buffer circuit and one of the first conductive paths;

a second buffer circuit; and

a second transistor coupled between the second buffer circuit and one of the second conductive paths.

3. An apparatus comprising:

a substrate;

a first memory cell block including first memory cell strings located over the substrate, and first data lines coupled to the first memory cell strings;

a second memory cell block including second memory cell strings located over the first memory cell block, the first memory block being physically located between the second memory block and the substrate, and second data lines coupled to the second memory cell strings, the first data lines being physically located between the second memory block and the substrate;

first conductive paths located over the substrate and coupled between the first data lines and buffer circuitry of the apparatus; and

second conductive paths located over the substrate and coupled between the second data lines and the buffer circuitry, wherein no conductive path of the first and second conductive paths is shared by the first and second memory cell blocks, wherein the buffer circuitry includes:

a buffer circuit;

a first transistor coupled between the buffer circuit and one of the first conductive paths; and

a second transistor coupled between the buffer circuit and one of the second conductive paths.

4. An apparatus comprising:

a substrate;

a first memory cell block including first memory cell strings located over the substrate, and first data lines coupled to the first memory cell strings;

a second memory cell block including second memory cell strings located over the first memory cell block, and second data lines coupled to the second memory cell strings;

first conductive paths located over the substrate and coupled between the first data lines and buffer circuitry of the apparatus;

second conductive paths located over the substrate and coupled between the second data lines and the buffer circuitry, wherein no conductive path of the first and second conductive paths is shared by the first and second memory cell blocks;

a first source select line coupled to each of the first memory cell strings, the first source select line to control first select transistors, each of the first select transistors being located along a segment of a respective pillar among pillars of the first memory cell strings;

a second source select line coupled to each of the second memory cell strings, the second source select line to control second select transistors, each of the second select transistors being located along a segment of a respective pillar among pillars of the second memory cell strings;

a first additional conductive path coupled to the first source select line and a driver circuit; and

a second additional conductive path coupled to the second source select line and the driver circuit, wherein the first additional conductive path is separate from the second additional conductive path.

5. An apparatus comprising:

a substrate;

a first memory cell block including first memory cell strings located over the substrate, and first data lines coupled to the first memory cell strings;

a second memory cell block including second memory cell strings located over the first memory cell block, and second data lines coupled to the second memory cell strings;

first conductive paths located over the substrate and coupled between the first data lines and buffer circuitry of the apparatus;

second conductive paths located over the substrate and coupled between the second data lines and the buffer circuitry, wherein no conductive path of the first and second conductive paths is shared by the first and second memory cell blocks;

a first conductive line contacting a pillar of each of the first memory cell strings;

a second conductive line contacting a pillar of each of the second of memory cell strings;

a first additional conductive path coupled to the first conductive line and a driver circuit; and

a second additional conductive path coupled to the second conductive line and the driver circuit, wherein the first additional conductive path is separate from the second additional conductive path.

6. An apparatus comprising:

a substrate;

a first memory cell block including first memory cell strings located over the substrate, and first data lines coupled to the first memory cell strings;

a second memory cell block including second memory cell strings located over the first memory cell block, and second data lines coupled to the second memory cell strings;

first conductive paths located over the substrate and coupled between the first data lines and buffer circuitry of the apparatus;

second conductive paths located over the substrate and coupled between the second data lines and the buffer circuitry, wherein no conductive path of the first and second conductive paths is shared by the first and second memory cell blocks;

a first deck of memory cell strings located over the substrate, the first deck of memory cell strings being physically located in a first portion of a memory device of the apparatus, the first deck of memory cell strings including a first plurality memory cell blocks physically located in the first portion of the memory device, wherein the first memory cell block is included in the first plurality memory cell blocks; and

a second deck of memory cell strings located over the first deck of memory cell strings, the second deck of memory cell strings being physically located between the second portion of the memory device and the substrate, the second deck of memory cell strings including a second plurality memory cell blocks physically located in the second portion of the memory device, wherein the second memory cell block is included in the second plurality memory cell blocks.

7. An apparatus comprising:

decks of memory cell strings including a first deck of first memory cell strings located over a substrate, and second deck of second memory cell strings located over the first deck of first memory cell strings, the first deck of memory cell strings being physically located in a first portion of a memory device of the apparatus, the second deck of memory cell strings being physically located in a second portion of the memory device, the first portion of the memory device being physically located between the second portion of the memory device and the substrate;

access lines coupled to the decks of memory cell strings;

data lines coupled to the decks of memory cell strings, wherein no deck of memory cell strings of the decks of memory cell strings shares an access line of the access lines with another deck of memory cell strings of the decks of memory cell strings, and no deck of memory cell strings of the decks of memory cell strings shares a data line of the data lines with another deck of memory cell strings of the decks of memory cell strings;

first transistors, each of the first transistors coupled to a respective access line of first access lines among the access lines;

second transistors, each of the second transistors coupled to a respective access line of second access lines among the access lines, wherein the first transistors include a first common gate, and the second transistors include a second common gate different from the first common gate; and

a decoder to concurrently turn on the first and second transistors during a memory operation of the apparatus.

8. An apparatus comprising:

decks of memory cell strings including a first deck of first memory cell strings located over a substrate, and second deck of second memory cell strings located over the first deck of first memory cell strings;

access lines coupled to the decks of memory cell strings;

data lines coupled to the decks of memory cell strings, wherein no deck of memory cell strings of the decks of memory cell strings shares an access line of the access lines with another deck of memory cell strings of the decks of memory cell strings, and no deck of memory cell strings of the decks of memory cell strings shares a data line of the data lines with another deck of memory cell strings of the decks of memory cell strings;

first transistors, each of the first transistors coupled to a respective access line of first access lines among the access lines;

second transistors, each of the second transistors coupled to a respective access line of second access lines among the access lines, wherein the first transistors include a first common gate, and the second transistors include a second common gate different from the first common gate; and

a decoder to turn on the first transistors during a memory operation of the apparatus, and turn off the second transistors while the first transistors are turned on during the memory operation.

9. An apparatus comprising:

decks of memory cell strings including a first deck of first memory cell strings located over a substrate, and second deck of second memory cell strings located over the first deck of first memory cell strings, the first deck of memory cell strings being physically located in a first portion of a memory device of the apparatus, the second deck of memory cell strings being physically located in a second portion of the memory device, the first portion of the memory device being physically located between the second portion of the memory device and the substrate;

access lines coupled to the decks of memory cell strings; and

data lines coupled to the decks of memory cell strings, wherein no deck of memory cell strings of the decks of memory cell strings shares an access line of the access lines with another deck of memory cell strings of the decks of memory cell strings, and no deck of memory cell strings of the decks of memory cell strings shares a data line of the data lines with another deck of memory cell strings of the decks of memory cell strings;

first conductive paths located over a substrate and coupled to first data lines among the data lines;

second conductive paths located over the substrate and coupled to second data lines among the data lines, wherein the first conductive paths are separate from the second conductive paths;

a decoder to concurrently couple the first conductive paths and the second conductive paths to circuitry in the substrate during a memory operation of the apparatus.

10. An apparatus comprising:

decks of memory cell strings including a first deck of first memory cell strings located over a substrate, and second deck of second memory cell strings located over the first deck of first memory cell strings;

access lines coupled to the decks of memory cell strings;

data lines coupled to the decks of memory cell strings, wherein no deck of memory cell strings of the decks of memory cell strings shares an access line of the access lines with another deck of memory cell strings of the decks of memory cell strings, and no deck of memory cell strings of the decks of memory cell strings shares a data line of the data lines with another deck of memory cell strings of the decks of memory cell strings;

first conductive paths located over a substrate and coupled to first data lines among the data lines;

second conductive paths located over the substrate and coupled to second data lines among the data lines, wherein the first conductive paths are separate from the second conductive paths; and

a decoder to couple the first conductive paths to circuitry in the substrate during a memory operation of the apparatus, and not to couple the second conductive paths to the circuitry in the substrate during the memory operation.