Semiconductor devices and methods of fabrication
Some embodiments include a semiconductor device having a stack structure including a source comprising polysilicon, an etch stop of oxide on the source, a select gate source on the etch stop, a charge storage structure over the select gate source, and a select gate drain over the charge storage structure. The semiconductor device may further include an opening extending vertically into the stack structure to a level adjacent to the source. A channel comprising polysilicon may be formed on a side surface and a bottom surface of the opening. The channel may contact the source at a lower portion of the opening, and may be laterally separated from the charge storage structure by a tunnel oxide. A width of the channel adjacent to the select gate source is greater than a width of the channel adjacent to the select gate drain.
1. A semiconductor device, comprising:
a stack structure including,
a source,
a select gate source level over the source,
a charge storage structure over the select gate source level,
a select gate drain level over the charge storage structure, and
an opening defined in the stack structure, the opening extending vertically into the stack structure to a level adjacent the source; and
a channel material comprising polysilicon formed over a side surface and a bottom surface defining the opening, the channel material contacting the source at a lower portion of the opening, and being laterally separated from the charge storage structure by a tunnel dielectric, wherein a first width of the channel material adjacent the charge storage structure is substantially the same as a second width of the channel material adjacent the select gate drain level; and
a conductive plug extending into the channel material from an upper surface of the channel material to a level lower than an upper surface of the select gate drain level.
2. The semiconductor device of claim 1 , wherein the charge storage structure is one of a plurality of charge storage structures in the stack structure, and wherein the second width of the opening adjacent the select gate drain level is substantially the same as a width of the opening adjacent the plurality of charge storage structures.
3. The semiconductor device of claim 1 , wherein the source comprises polysilicon.
4. The semiconductor device of claim 1 , wherein the conductive plug extends from the upper surface of the channel material to a level adjacent a lower surface of the select gate drain level.
5. The semiconductor device of claim 1 , wherein the conductive plug extends from the upper surface of the channel material to a level adjacent the charge storage structure.
6. The semiconductor device of claim 1 , wherein the charge storage structure comprises a floating gate.