Apparatuses and methods for operations in a self-refresh state

1. An apparatus, comprising:

an array of memory cells; and

a controller, coupled to the array, configured to direct performance of logical operations on data stored in the memory cells of the array when the array is in a self-refresh state; wherein:

a logical operation is performed on a first data value read using a sense line coupled to a memory cell in the array in combination with a second data value stored in sensing circuitry coupled to the array; and

the first data value is retrieved from a first memory cell of the array and the second data value is retrieved from a second memory cell of the array.

2. The apparatus of claim 1 , wherein:

the apparatus further comprises a host; and

input/output circuitry between the controller and the host is idle during the performance of the logical operations in the self-refresh state.

3. The apparatus of claim 1 , wherein:

the apparatus further comprises a counter register that controls a frequency of performance of a memory refresh cycle for the data stored in the memory cells; and

refresh signals are not received from a host during the performance of the logical operations in the self-refresh state.

4. The apparatus of claim 3 , wherein the apparatus further comprises the counter register being coupled to the controller.

5. The apparatus of claim 3 , wherein the apparatus further comprises the counter register being coupled to the array.

6. The apparatus of claim 1 , wherein the controller is configured to direct the performance of the logical operations at a rate corresponding to a frequency of performance of a memory refresh cycle for the data stored in the memory cells.

7. The apparatus of claim 1 , wherein a logical operation is performed on the data using the sensing circuitry during performance of a self-refresh operation by the sensing circuitry on the data.

8. A method for operating a memory device, comprising:

selecting from a plurality of modes for performance of logical operations;

performing the logical operations corresponding to the selected mode on a first data value stored in a first memory cell and a second data value stored in a second memory cell of the memory device when the memory device is in a self-refresh state; and

performing a logical operation on the first data value retrieved from the first memory cell in combination with the second data value retrieved from the second memory cell and stored in sensing circuitry of the memory device;

wherein the logical operation is performed using a sense amplifier coupled to a compute component, in the sensing circuitry, configured to read the first data value and store the second data value.

9. The method of claim 8 , wherein the method further includes:

adjusting a frequency of performance of a memory refresh cycle for the data stored in the memory cells; and

performing the logical operations at a rate corresponding to the adjusted frequency of performance of the memory refresh cycle.

10. The method of claim 9 , wherein performing a logical operation comprises sensing data in a memory cell with a sense amplifier.

11. The method of claim 8 , wherein performing the logical operations comprises controlling each logical operation to correspond to a period of a counter register that controls a frequency of performance of a memory refresh cycle for the data stored in the memory cells.

12. The method of claim 8 , wherein performing the logical operations in the self-refresh state comprises performing a logical operation in which high latency is not a burden.

13. The method of claim 8 , wherein the method further includes performing the logical operations without interaction with a host.

14. The method of claim 8 , wherein performing the logical operations in the self-refresh state comprises performing a processing in memory (PIM) operation to provide a result that is accessible when the memory device is not in the self-refresh state and is interacting with a host.