Performing logical operations using sensing circuitry

1. An apparatus, comprising:

an array of memory cells;

sensing circuitry coupled to the array of memory cells via a sense line, the sensing circuitry including a sense amplifier; and

a controller coupled to the array of memory cells and the sensing circuitry, the controller being configured to:

perform logical operations using the array of memory cells as an accumulator without transferring data out of the memory array and sensing circuitry, wherein an operand of the logical operations is stored in the accumulator throughout the performance of the logical operations.

2. The apparatus of claim 1 , wherein the apparatus is configured to perform logical operations using the array of memory cells for storage of operands of the logical operations.

3. The apparatus of claim 1 , wherein the apparatus is configured to always sense a particular data value as a result of an AND logical operation when the particular data value is sensed for the operand.

4. The apparatus of claim 1 , wherein the apparatus is configured to always sense a particular data value as a result of an OR logical operation when the particular data value is sensed for the operand.

5. The apparatus of claim 1 , wherein the apparatus is configured to modify voltage of the sense line to an extent that a charge of the memory cell storing another operand is not sufficient to change a data value represented by the modified voltage of the sense line.

6. An apparatus, comprising:

an array of memory cells; and

a sense amplifier coupled to the array of memory cells via a sense line; and

a controller coupled to the array of memory cells,

wherein the controller is configured to:

apply a voltage to a plurality of access lines coupled to the array sufficient to cause access devices coupled thereto to be turned-on responsive to memory cells of the array to which the access devices correspond storing a first data value, and insufficient to cause the access devices coupled thereto to be turned-on responsive to memory cells of the array to which the access devices correspond storing a second data value; and

couple a memory cell storing a charge corresponding to an operand of a logical operation to the sense line after applying the voltage to the plurality of access without performing an equilibration operation after applying the voltage to the plurality of access lines.

7. The apparatus of claim 6 , wherein the voltage applied to the plurality of access lines is equal to a sense line equilibration voltage plus a portion of a threshold voltage of the access devices.

8. The apparatus of claim 6 , wherein the voltage applied to the plurality of access lines is within a voltage range from a threshold voltage of the access devices to the threshold voltage of the access devices plus an equilibration voltage.

9. The apparatus of claim 6 , wherein the logical operation is an AND logical operation, wherein the controller is configured to sense a voltage of the sense line after coupling of the memory cell to the sense line, and wherein the voltage of the sense line corresponds to a result of the AND logical operation.

10. A method, comprising:

charging different access lines to within a voltage to which a sense line is charged plus some portion of a threshold voltage of a memory cell access device coupled to the sense line and the different access lines; and

modifying a voltage of the sense line with a charge stored in a memory cell coupled to the sense line and to an access line other than the different access lines, the charge corresponding to an operand of a logical operation, and the modified voltage of the sense line indicating a result of the logical operation.

11. The method of claim 10 , further comprising equilibrating the sense line to an equilibrate voltage prior to charging the different access lines, wherein charging the different access lines includes charging the different access lines to the equilibrate voltage.

12. The method of claim 10 , further comprising equilibrating the sense line to an one half of a supply voltage prior to charging the different access lines, wherein charging the different access lines includes charging the different access lines to one half of the supply voltage.

13. The method of claim 10 , further comprising:

isolating the memory cell from the sense line; and

equilibrating the sense line to an equilibration voltage after isolating the memory cell from the sense line and prior to charging the different access lines.

14. The method of claim 10 , further comprising isolating the memory cell coupled to the sense line and to different access lines.

15. The method of claim 10 , wherein charging the different access lines includes charging the different access lines to within a voltage range from the threshold voltage of the memory cell access device to the threshold voltage of the memory cell access device plus a voltage to which the sense line is charged.

16. The method of claim 10 , wherein charging the different access lines includes charging the different access lines to within a voltage range from the threshold voltage of the memory cell access device to the threshold voltage of the memory cell access device plus a sense line equilibration voltage.

17. The method of claim 10 , wherein charging the different access lines includes charging the different access lines to within a voltage range from the threshold voltage of the memory cell access device to the threshold voltage of the memory cell access device plus one-half of a power supply voltage.

18. The method of claim 10 , wherein charging the different access lines includes charging the different access lines to a same voltage as the sense line plus one half of the threshold voltage of the memory cell access device.

19. The method of claim 10 , wherein charging the different access lines includes charging the different access lines to a sense line equilibration voltage plus one-half of the threshold voltage of the memory cell access device.

20. The method of claim 10 , wherein the logical operation is an AND logical operation, wherein the method further comprises sensing the voltage of the sense line, and wherein the voltage of the sense line corresponds to a result of the logical operation.