IP Library Granted Patent US 9,887,083
Granted Patent B2
US 9,887,083 · App. 14/877,677 · Granted Feb 6, 2018

Methods of forming capacitors

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Quick Facts
Patent No.
US 9,887,083
App. No.
14/877,677
Granted
Feb 6, 2018
Kind
B2
Abstract

A method of forming a capacitor includes depositing a dielectric metal oxide layer of a first phase to a thickness no greater than 75 Angstroms over an inner conductive capacitor electrode material. The first phase dielectric metal oxide layer has a k of at least 15. Conductive RuO 2 is deposited over and into physical contact with the dielectric metal oxide layer. Then, the RuO 2 and the dielectric metal oxide layer are annealed at a temperature below 500° C. The RuO 2 in physical contact with the dielectric metal oxide during the annealing facilitates a change of the dielectric metal oxide layer from the first phase to a second crystalline phase having a higher k than the first phase. The annealed dielectric metal oxide layer is incorporated into a capacitor dielectric region of a capacitor construction. Other implementations are disclosed.

Claims (14)

1. A method of forming a capacitor, comprising:

depositing conductive capacitor electrode material over a substrate;

depositing a dielectric metal oxide layer over and into physical contact with the conductive capacitor electrode material;

depositing RuO 2 over the dielectric metal oxide layer;

annealing the inner conductive capacitor electrode, the RuO 2 and the dielectric metal oxide layer;

after the annealing and prior to any subsequent processing, etching utilizing an etch chemistry comprising O 3 to selectively remove at least some of the RuO 2 ; and

after the etching, forming conductive capacitor electrode material over the dielectric metal oxide layer.

2. A method of forming a capacitor, comprising:

depositing conductive capacitor electrode material over a substrate;

depositing a dielectric metal oxide layer over and into physical contact with the conductive capacitor electrode material;

depositing RuO 2 over the dielectric metal oxide layer;

annealing the inner conductive capacitor electrode, the RuO 2 and the dielectric metal oxide layer;

after the annealing, etching utilizing an etch chemistry comprising O 3 to selectively remove at least some of the RuO 2 , the etch chemistry comprising a mixture consisting of O 2 and O 3 , and wherein the mixture contains from 18% to 22% O 3 , by volume; and

after the etching, forming conductive capacitor electrode material over the dielectric metal oxide layer.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050680/0268 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 2 TO PATENT SECURITY AGREEMENT Recorded Feb 10, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041671/0902 →