Integrated structures and methods of forming vertically-stacked memory cells

1. A method of forming vertically-stacked memory cells, comprising:

forming a first insulative material over a stack of alternating dielectric levels and conductive levels;

forming a first opening through the first insulative material and through the stack of alternating dielectric levels and conductive levels;

forming cavities extending into the conductive levels along sidewalls of the first opening;

forming a silicon nitride liner within the first opening and extending into the cavities;

forming a second insulative material over the silicon nitride liner and over the first insulative material, the second insulative material covering the first opening and not extending downwardly into the first opening to an uppermost level of the stack, a remaining portion of the first opening being beneath the second insulative material;

forming select gate material over the second insulative material;

forming a second opening the through the select gate material and the second insulative material, and to the remaining portion of the first opening, the first and second openings joining with one another and together forming a third opening; and

after forming the third opening:

forming charge-storage structures within the cavities;

removing regions of the silicon nitride liner that are not within the cavities; and

forming channel material within the third opening and adjacent the second insulative material, adjacent the select gate material, adjacent the dielectric levels of the stack, and adjacent the charge-storage structures.

2. The method of claim 1 wherein the second insulative material comprises silicon dioxide and is formed utilizing plasma-enhanced chemical vapor deposition.

3. The method of claim 1 wherein the select gate material is drain-side select gate material; wherein the drain-side select gate material and the charge-storage structures comprise silicon, and further comprising oxidizing exposed surfaces of the drain-side select gate material and the charge storage structures prior to forming the channel material; the oxidized surfaces of the charge-storage structures forming gate dielectric.

4. The method of claim 1 wherein the third opening has a first region within the second insulative material, a second region of the opening within the select gate material, and a third region within the stack of alternating dielectric levels and conductive levels; and wherein the first, second and third regions are all about the same width as one another along a cross-section.

5. The method of claim 1 wherein the third opening has a first region within the second insulative material, a second region within the select gate material, and a third region within the stack of alternating dielectric levels and conductive levels; and wherein the first region is wider than the second and third regions along a cross-section.

6. The method of claim 5 wherein the wherein the first region is wider than the second and third regions by an amount within a range of from about 3 nm to about 25 nm.

7. A method of forming vertically-stacked memory cells, comprising:

forming an opening which extends through a select gate material, through an insulative material under the select gate material, and through a stack of alternating dielectric levels and conductive levels under the insulative material; the stack including memory cells within the conductive levels; a first region of the opening within the insulative material being wider along a cross-section than a second region of the opening within the select gate material, and being wider along the cross-section than a third region of the opening within the stack of alternating dielectric levels and conductive levels; and

forming channel material within the opening adjacent the insulative material, adjacent the select gate material, adjacent the dielectric levels of the stack, and adjacent the memory cells.

8. The method of claim 7 wherein the insulative material comprises silicon dioxide and is formed utilizing plasma-enhanced chemical vapor deposition.

9. The method of claim 7 wherein the second and third regions of the opening are about a same width as one another along the cross-section.

10. The method of claim 7 wherein the first region is wider than the second and third regions by an amount within a range of from about 3 nm to about 25 nm.

11. The method of claim 7 wherein the first region has a width along the cross-section within a range of from about 60 nm to about 75 nm, and wherein second and third regions have widths along the cross-section within a range of from about 55 nm to about 65 nm.

12. The method of claim 7 wherein the select gate material is drain-side select gate material; wherein the opening extends through a source-side select gate material and to a conductive source material; and wherein the channel material is formed to be a continuous layer adjacent the drain-side select gate material, insulative material, dielectric levels of the stack, memory cells, source-side select gate material and conductive source material.