Memory including a selector switch on a variable resistance memory cell
Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a selector switch in direct contact with the memory cell, and configured to facilitate access to the memory cell. Other embodiments may be described and claimed.
1. A method of forming a memory device, comprising:
forming a memory cell coupled with a bit line and a word line;
forming a selector switch in contact with and disposed on a portion of the memory cell;
forming a sealing layer in contact with an upper surface and a pair of sidewalls of the selector switch and a pair of sidewalls of the memory cell;
forming a first conductive plug in contact with and disposed on a portion of an upper surface of the sealing layer;
forming a first diffusion layer in contact with a pair of sidewalls of the first conductive plug;
forming a second conductive plug in contact with a lower surface of the memory cell; and
forming a second diffusion layer in contact with a pair of sidewalls of the second conductive plug.
2. The method of claim 1 , wherein the selector switch comprises a Schottky diode.
3. The method of claim 1 , wherein forming the selector switch is based at least in part on a thermal budget of less than 150° C.
4. The method of claim 1 , wherein the memory cell comprises a variable resistance memory material.
5. The method of claim 1 , wherein the first conductive plug is configured to pass electrical current between the selector switch and the word line.
6. The method of claim 1 , wherein the second conductive plug is configured to pass electrical current between the memory cell and the bit line.
7. An apparatus comprising:
a selector switch in contact with a memory cell;
a sealing layer in contact with an upper surface and a pair of sidewalls of the selector switch and a pair of sidewalls of the memory cell;
a first conductive plug in contact with and disposed on a portion of the sealing layer;
a first diffusion layer in contact with and disposed on a pair of sidewalls of the first conductive plug;
a second conductive plug in contact with a lower surface of the memory cell; and
a second diffusion layer in contact with a pair of sidewalls of the second conductive plug.
8. The apparatus of claim 7 , wherein the memory cell comprises an upper electrode layer, a lower electrode layer, and a variable resistance memory layer.
9. The apparatus of claim 8 , wherein the variable resistance memory layer is disposed between the upper electrode layer and the lower electrode layer.
10. The apparatus of claim 7 , wherein the selector switch comprises a first metal layer and a first non-silicon-based semiconductor layer in contact with an upper surface of the first metal layer.
11. The apparatus of claim 10 , wherein the selector switch comprises a second metal layer and a second non-silicon-based semiconductor layer disposed between the first non-silicon-based semiconductor layer and the second metal layer, the second non-silicon-based semiconductor layer in contact with an upper surface of the first non-silicon-based semiconductor layer and a lower surface of the second metal layer.
12. The apparatus of claim 11 , wherein the first metal layer comprises a first metal material and the second metal layer comprises a second metal material.
13. The apparatus of claim 12 , wherein the first metal material and the second metal material are same.
14. The apparatus of claim 12 , wherein the first metal material and the second metal material are different.
15. The apparatus of claim 12 , wherein the first metal material and the second metal material comprise a material selected from the group consisting of silver, platinum, carbon, aluminum, titanium, nickel, gold, and aluminum.
16. A system comprising:
a host logic device bus; and
a flash memory device coupled to the host logic device bus, the flash memory device comprising:
a memory cell;
a selector switch in contact with the memory cell;
a sealing layer in contact with the memory cell and the selector switch;
a plurality of dielectric layers in contact with a portion of the memory cell and the selector switch;
a first conductive plug in contact with the sealing layer and configured to pass current between the selector switch and a word line;
a first diffusion layer in contact with and on a pair of sidewalls of the first conductive plug;
a second conductive plug in contact with the memory cell and configured to pass current between the memory cell and a bit line; and
a second diffusion layer in contact with a pair of sidewalls of the second conductive plug.
17. The system of claim 16 , wherein the memory cell further comprises a first carbon electrode layer, a second carbon electrode layer, and a variable resistance memory layer disposed between the first and second carbon electrode layers.
18. The system of claim 17 , wherein the selector switch comprises a semiconductor oxide associated with a deposition temperature below a melting temperature of the variable resistance memory layer.
19. The system of claim 16 , wherein the sealing layer intersects adjacent dielectric layers of the plurality of dielectric layers.
20. The system of claim 16 , wherein the flash memory device comprises phase change memory.