Memory including a selector switch on a variable resistance memory cell
Embodiments include but are not limited to apparatuses and systems including memory having a memory cell including a variable resistance memory layer, and a selector switch in direct contact with the memory cell, and configured to facilitate access to the memory cell. Other embodiments may be described and claimed.
1. An apparatus comprising:
a memory cell comprising:
a first carbon electrode layer;
a second carbon electrode layer; and
a variable resistance memory layer disposed between the first and second carbon electrode layers;
a semiconductor-oxide-based, non-silicon selector switch in direct contact with the memory cell;
a sealing layer in contact with both the memory cell and the semiconductor-oxide-based, non-silicon selector switch;
a plurality of dielectric layers that partially surround the memory cell, the semiconductor-oxide-based, non-silicon selector switch, and the sealing layer, wherein the plurality of dielectric layers are in direct contact with at least the memory cell and the sealing layer, and wherein the sealing layer separates adjacent dielectric layers of the plurality of dielectric layers;
a word line conductive plug located on the sealing layer and configured to allow electrical access between the semiconductor-oxide-based, non-silicon selector switch and a word line;
a bit line conductive plug located on the memory cell and configured to allow electrical access between the memory cell and a bit line;
a first diffusion barrier layer at least partially surrounding the word line conductive plug; and
a second diffusion barrier at least partially surrounding the bit line conductive plug.
2. The apparatus of claim 1 , wherein the semiconductor-oxide-based, non-silicon selector switch comprises a zinc oxide layer and a contact layer comprising silver, platinum, carbon, aluminum, titanium, or nickel.
3. The apparatus of claim 1 , wherein the semiconductor-oxide-based, non-silicon selector switch comprises a semiconductor oxide having a deposition temperature below a melting temperature of the variable resistance memory layer.
4. The apparatus of claim 1 , wherein the semiconductor-oxide-based, non-silicon selector switch comprises a p-type zinc oxide layer and an n-type zinc oxide layer, wherein the semiconductor-oxide-based, non-silicon selector switch further comprises a first contact layer and a second contact layer, and wherein the p-type zinc oxide layer and the n-type zinc oxide layer are disposed between the first contact layer and the second contact layer.
5. The apparatus of claim 4 , wherein at least one of the first contact layer and the second contact layer comprises silver, platinum, carbon, aluminum, titanium, nickel, gold, or aluminum.
6. The apparatus of claim 4 , wherein the first contact layer comprises silver and the second contact layer comprises a titanium and gold alloy.
7. The apparatus of claim 1 , wherein the variable resistance memory layer comprises an organic material selected from the group including a self-assembled mono-layer, an organic-metal-organic complex, and a bulk organic semiconductor having single molecules, oligomers, or polymers.
8. The apparatus of claim 1 , wherein the variable resistance memory layer comprises a chalcogenide.
9. The apparatus of claim 1 , wherein the first and second conductive plugs comprise tungsten.
10. A flash memory device comprising:
a memory cell comprising:
a first carbon electrode layer;
a second carbon electrode layer; and
a variable resistance memory layer disposed between the first and second carbon electrode layers;
a semiconductor-oxide-based, non-silicon selector switch in direct contact with the memory cell;
a sealing layer in contact with both the memory cell and the semiconductor-oxide-based, non-silicon selector switch;
a plurality of dielectric layers that partially surround the memory cell, the semiconductor-oxide-based, non-silicon selector switch, and the sealing layer, wherein the plurality of dielectric layers are in direct contact with at least the memory cell and the sealing layer, and wherein the sealing layer separates adjacent dielectric layers of the plurality of dielectric layers;
a word line conductive plug located on the sealing layer and configured to allow electrical access between the semiconductor-oxide-based, non-silicon selector switch and a word line;
a bit line conductive plug located on the memory cell and configured to allow electrical access between the memory cell and a bit line;
a first diffusion barrier layer at least partially surrounding the word line conductive plug; and
a second diffusion barrier at least partially surrounding the bit line conductive plug.
11. The flash memory device of claim 10 , wherein the flash memory device comprises phase change memory.
12. The flash memory device of claim 10 , wherein the variable resistance memory layer comprises a chalcogenide.
13. The flash memory device of claim 10 , wherein the semiconductor-oxide-based, non-silicon selector switch comprises a p-type zinc oxide layer and an n-type zinc oxide layer, wherein the semiconductor-oxide-based, non-silicon selector switch further comprises a first contact layer and a second contact layer, and wherein the p-type zinc oxide layer and the n-type zinc oxide layer are disposed between the first contact layer and the second contact layer.
14. A system comprising:
a host logic device bus;
a flash memory device coupled to the host logic device bus, the flash memory device comprising:
a memory cell comprising:
a first carbon electrode layer;
a second carbon electrode layer; and
a variable resistance memory layer disposed between the first and second carbon electrode layers;
a semiconductor-oxide-based, non-silicon selector switch in direct contact with the memory cell;
a sealing layer in contact with both the memory cell and the semiconductor-oxide-based, non-silicon selector switch;
a plurality of dielectric layers that partially surround the memory cell, the semiconductor-oxide-based, non-silicon selector switch, and the sealing layer, wherein the plurality of dielectric layers are in direct contact with at least the memory cell and the sealing layer, and wherein the sealing layer separates adjacent dielectric layers of the plurality of dielectric layers;
a word line conductive plug located on the sealing layer and configured to allow electrical access between the semiconductor-oxide-based, non-silicon selector switch and a word line;
a bit line conductive plug located on the memory cell and configured to allow electrical access between the memory cell and a bit line;
a first diffusion barrier layer at least partially surrounding the word line conductive plug; and
a second diffusion barrier at least partially surrounding the bit line conductive plug.
15. The system of claim 14 , wherein the host logic device bus comprises a plurality of processor cores.
16. The system of claim 14 , wherein the system is selected from the group consisting of a set-top box, a digital recorder, a game console, a personal digital assistant, a mobile phone, a digital media player, or a digital camera.
17. The system of claim 14 , wherein the flash memory device comprises phase change memory.
18. The system of claim 14 , wherein the variable resistance memory layer comprises an organic material selected from the group including a self-assembled mono-layer, an organic-metal-organic complex, and a bulk organic semiconductor having single molecules, oligomers, or polymers.
19. The system of claim 14 , wherein the semiconductor-oxide-based, non-silicon selector switch comprises a zinc oxide layer and a contact layer comprising silver, platinum, carbon, aluminum, titanium, or nickel.
20. The system of claim 14 , wherein the semiconductor-oxide-based, non-silicon selector switch comprises a semiconductor oxide having a deposition temperature below a melting temperature of the variable resistance memory layer.