Apparatus and method for instant-on quadra-phase signal generator

1. An apparatus comprising:

a first delay circuit configured to receive a first input clock signal and generate a first delayed clock signal, the first delay circuit configured to adjust a delay of the first delayed clock signal based, at least in part, on a period of the first input clock signal; and

a first phase mixer coupled to the first delay circuit and configured to:

receive the first delayed clock signal at a first input and a second input clock signal at a second input, and

generate a first output clock signal at a first output node responsive, at least in part, to mixing of the first delayed clock signal and the second input clock signal.

2. The apparatus of claim 1 , further comprising:

a second delay circuit configured to receive the second input clock signal and generate a second delayed clock signal; and

a second phase mixer coupled to the second delay circuit and configured to:

receive the second delayed clock signal at a third input and the first input clock signal at a fourth input, and

generate a second output clock signal at a second output node responsive, at least in part, to mixing of the second delayed clock signal and the first input clock signal.

3. An apparatus comprising:

a first delay circuit configured to receive a first input clock signal and generate a first delayed clock signal,

a first phase mixer coupled to the first delay circuit and configured to:

receive the first delayed clock signal at a first input and a second input clock signal at a second input, and

generate a first output clock signal at a first output node responsive, at least in part, to mixing of the first delayed clock signal and the second input clock signal:

a second delay circuit configured to receive the second input clock signal and generate a second delayed clock signal;

a second phase mixer coupled to the second delay circuit and configured to:

receive the second delayed clock signal at a third input and the first input clock signal at a fourth input, and

generate a second output clock signal at a second output node responsive, at least in part, to mixing of the second delayed clock signal and the first input clock signal; and

a first buffer and a second buffer, wherein

the first delay circuit is further configured to generate a third delayed clock signal, wherein the third delayed clock signal is smaller in delay amount than the first delayed clock signal,

the second delay circuit is further configured to generate a fourth delayed clock signal, wherein the fourth delayed clock signal is smaller in delay amount than the second delayed clock signal,

the first buffer is configured to generate a third output clock signal based on the third delayed clock signal, and

the second buffer is configured to generate a fourth output clock signal based on the fourth delayed clock signal.

4. The apparatus of claim 3 , wherein each of the first phase mixer and the second phase mixer is configured to have a first propagation delay, and wherein each of the first and second delay buffers is configured to have a second propagation delay that is the same as the first propagation delay.

5. The apparatus of claim 3 , wherein the first output clock signal corresponds to a 90-degree phase output clock signal, the second output clock signal corresponds to a 270-degree phase output clock signal, the third output clock signal corresponds to a 0-degree phase output clock signal, and the fourth output clock signal corresponds to a 180-degree phase output clock signal.

6. The apparatus of claim 1 , wherein the first input and the second input of the first phase mixer are weighted equally to be mixed at the first common output node.

7. The apparatus of claim 1 , wherein the delay of the first delay circuit is configured to be greater than or equal to ¼ of the period of the first input clock signal.

8. The apparatus of claim 1 , wherein the delay of the first delay circuit is configured to be less than or equal to one full period of the first input clock signal.

9. An apparatus comprising:

at least one delay circuit configured to generate at least a first delayed clock signal, a second delayed clock signal being smaller in delay amount than the first delayed clock signal, a third delayed clock signal, and a fourth delayed clock signal; and

at least one phase mixer coupled to the at least one delay circuit, wherein the at least one phase mixer is configured to:

generate a first output clock signal responsive, at least in part, to mixing of the first delayed clock signal and a second input clock signal, and

generate a second output clock signal responsive, at least in part, to mixing the third delayed clock signal and a first input clock signal.

10. The apparatus of claim 9 , further comprising a delay matching block, wherein the delay matching block is configured to generate a third output clock signal and a fourth output clock signal, wherein the third output clock signal is responsive at least in part, to the second delayed clock signal and a propagation delay of the at least one phase mixer, and wherein the fourth output clock signal is responsive, at least in part, to the fourth delayed clock signal and the propagation delay.

11. The apparatus of claim 10 , wherein each of: the first and third output clock signals; first and fourth output clock signals; second and third output clock signals; and second and fourth output clock signals are offset in phase by 90-degree.

12. The apparatus of claim 9 , wherein the first delayed clock signal and the second input clock signal are weighted equally when mixed to produce the first output clock signal, and wherein the third delayed clock signal and the first input clock signal are weighted equally when mixed to produce the second output clock signal.

13. The apparatus of claim 9 , wherein mixing, via the at least one phase mixer, includes at least one of additive or multiplicative mixing.

14. The apparatus of claim 9 , wherein the at least one phase mixer includes a first input and a second input, wherein the first input is coupled to a first inverter and the second input is coupled to a second inverter, wherein the output of the first and second controlled inverters are coupled to an output node.

15. An apparatus comprising:

a first delay circuit configured to receive a first input clock signal and generating a first delayed clock signal, wherein the first delay circuit is further configured to adjust the delay; and

a first phase mixer communicatively coupled to the first delay circuit and configured to:

receive the first delayed clock signal at a first input and a second input clock signal at a second input,

generate a first output clock signal at a first output node, wherein the first output clock signal is produced responsive, at least in part, to mixing of the first delayed clock signal and the second input clock signal.

16. The apparatus of claim 15 , further comprising:

a second delay circuit configured to receive the second input clock signal and generating a second delayed clock signal, wherein the second adjustable delay circuit is further configured to adjust the delay;

a second phase mixer communicatively coupled to the second delay circuit and configured to:

receive the second delayed clock signal at a first input and the first input clock signal at a second input,

generate a second output clock signal at a second output node, wherein the second output clock signal is produced responsive, at least in part, to mixing of the second delayed clock signal and the first input clock signal.

17. The apparatus of claim 15 , wherein the delay may be adjusted to be greater than or equal to ¼ of the period of the input clock signal and less than or equal to one full period of the input clock signal.

18. The apparatus of claim 17 , wherein adjustment of the delay is continuous, based on the period of the input clock signal.

19. The apparatus of claim 17 , wherein first delay circuit is configured to define two or more ranges, wherein each of the two or more ranges is associated with a range of input clock signal periods and assigned a respective delay, wherein the first delay circuit is configured to select the respective delay based, at least in part, on the period of the input clock signal being associated with a respective range of the two or more ranges.