IP Library Granted Patent US 10,452,598
Granted Patent B2
US 10,452,598 · App. 15/296,188 · Granted Oct 22, 2019

Apparatuses and methods for an operating system cache in a solid state device

Inventor: Juyoung Jung (Folsom, CA)
Assignee: Micron Technology, Inc.
G06F13/4282G06F12/0246G06F12/0866G06F13/28G06F2212/205G06F2212/214G06F2212/313G06F2212/604
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,452,598
App. No.
15/296,188
Granted
Oct 22, 2019
Kind
B2
Abstract

The present disclosure includes apparatuses and methods for an operating system cache in a solid state device (SSD). An example apparatus includes the SSD, which includes an In-SSD volatile memory, a non-volatile memory, and an interconnect that couples the non-volatile memory to the In-SSD volatile memory. The SSD also includes a controller configured to receive a request for performance of an operation and to direct that a result of the performance of the operation is accessible in the In-SSD volatile memory as an In-SSD main memory operating system cache.

Claims (52)

1. An apparatus, comprising:

a solid state device (SSD), wherein the SSD comprises:

an In-SSD volatile memory;

a non-volatile memory;

an interconnect that couples the non-volatile memory to the In-SSD volatile memory; and

a controller configured to:

receive a request for performance of an operation;

direct that a requested block of data be moved from a block address in the non-volatile memory to an In-SSD main memory (MM) operating system cache in the In-SSD volatile memory;

direct that a result of the performance of the operation is accessible in the In-SSD volatile memory as the In-SSD MM operating system cache;

notify a device driver, associated with an operating system, that the requested block of data is moved from the non-volatile memory to the In-SSD MM operating system cache in the In-SSD volatile memory; and

notify the operating system that the performance of the operation is completed.

2. The apparatus of claim 1 , wherein:

the request is received from a device driver; and

the device driver is associated with an operating system.

3. The apparatus of claim 1 , wherein:

the request comprises a block address for a block of data stored by the non-volatile memory; and

a device driver sends the request to the controller.

4. The apparatus of claim 1 , wherein the controller is further configured to selectably move the result of the operation from the In-SSD MM operating system cache of the In-SSD volatile memory to a host system.

5. The apparatus of claim 4 , wherein to selectably move the result of the operation comprises to select between:

movement of the result for storage in a cache of the host system; and

movement of the result to a cache internal to a processing resource of the host system, without being stored by the cache, to enable performance of a particular operation directed by the operating system.

6. The apparatus of claim 1 , wherein the performance of the operation comprises:

movement of data stored by the non-volatile memory to the In-SSD volatile memory; and

storage of the data in the In-SSD MM operating system cache.

7. The apparatus of claim 1 , wherein the apparatus further comprises:

an operating system configured as part of a host system, the host system comprising:

a central processing unit (CPU);

a host MM including a host volatile memory; and

an In-host MM operating system cache as part of the host volatile memory.

8. A method, comprising:

operating a solid state device (SSD), wherein the SSD comprises a controller that is configured to perform:

receiving a request for performance of an operation;

directing that a requested block of data be moved from a block address in a non-volatile memory to an In-SSD main memory (MM) operating system cache in an In-SSD volatile memory, wherein the data is moved using an interconnect that couples the non-volatile memory to the In-SSD volatile memory;

directing that a result of the performance of the operation is accessible in the In-SSD volatile memory as an In-SSD MM operating system cache;

notifying a device driver, associated with an operating system, that the requested block of data is moved from the non-volatile memory to the In-SSD MM operating system cache in the In-SSD volatile memory; and

notifying the operating system that the performance of the operation is completed.

9. The method of claim 8 , further comprising receiving the request from a device driver that is associated with an operating system.

10. The method of claim 8 , further comprising:

including in the request a block address for a block of data stored by the non-volatile memory; and

sending, by a device driver, the request to the controller.

11. The method of claim 8 , wherein the controller is further configured to perform selectably moving the result of the operation from the In-SSD MM operating system cache of the In-SSD volatile memory to a host system.

12. The method of claim 11 , wherein selectably moving the result of the operation comprises selecting between:

movement of the result for storage in a cache of the host system; and

movement of the result to a cache internal to a processing resource of the host system, without being stored by the cache, to enable performance of a particular operation directed by the operating system.

13. The method of claim 8 , wherein the performance of the operation comprises:

moving data stored by the non-volatile memory to the In-SSD volatile memory; and

storing the data in the In-SSD MM operating system cache.

14. The method of claim 8 , wherein:

operating the SSD further comprises using an operating system that is part of a host system, wherein the host system comprises:

a central processing unit (CPU);

a host MM including a host volatile memory; and

an In-host MM operating system cache as part of the host volatile memory.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050680/0268 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 2 TO PATENT SECURITY AGREEMENT Recorded Feb 10, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041671/0902 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 18, 2016
From: JUNG, JUYOUNG
To: MICRON TECHNOLOGY, INC.
Reel/Frame 040042/0315 →