IP Library Granted Patent US 9,837,383
Granted Patent B2
US 9,837,383 · App. 15/229,618 · Granted Dec 5, 2017

Interconnect structure with improved conductive properties and associated systems and methods

Inventors: Jaspreet S. Gandhi (Boise, ID); Wayne H. Huang (Boise, ID); James M. Derderian (Boise, ID)
Assignee: Micron Technology, Inc.
H01L25/0657H01L23/00H01L23/34H01L23/4012H01L23/49827H01L24/05H01L24/11H01L24/13H01L24/81H01L25/043H01L25/065H01L25/0756H01L25/50H01L23/3675H01L23/42H01L23/49811H01L2224/05599H01L2224/11H01L2224/13111H01L2224/13147H01L2224/13155H01L2224/16145H01L2224/16225H01L2224/16503H01L2224/73253H01L2224/81815H01L2225/06513H01L2225/06517H01L2225/06527H01L2225/06541H01L2225/06555H01L2225/06586H01L2225/06589H01L2924/0105H01L2924/01013H01L2924/01028H01L2924/01029H01L2924/01047H01L2924/01327H01L2924/05032H01L2924/15311H01L2924/181
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Quick Facts
Patent No.
US 9,837,383
App. No.
15/229,618
Granted
Dec 5, 2017
Kind
B2
Abstract

Interconnect structures with improved conductive properties are disclosed herein. In one embodiment, an interconnect structure can include a first conductive member coupled to a first semiconductor die and a second conductive member coupled to second semiconductor die. The first conductive member includes a recessed surface defining a depression. The second conductive member extends at least partially into the depression of the first conductive member. A bond material within the depression can at least partially encapsulate the second conductive member and thereby bond the second conductive member to the first conductive member.

Claims (26)

1. A method of forming a semiconductor die assembly, comprising:

forming a dielectric material on a second semiconductor die;

forming first openings in the dielectric material that expose underlying conductive features;

forming a mask on the dielectric material, wherein the mask includes second openings superimposed on the first openings such that portions of the dielectric material are exposed within the second openings;

depositing a conductive material on each of the conductive features and the portions of the dielectric material within the second openings, wherein the portions of the dielectric material are configured such that a plurality of depressions form in the conductive material in-situ with the deposition of the conductive material;

inserting at least a portion of a plurality of first conductive members on a first semiconductor die into at least a portion of the depressions in the corresponding conductive material on the second semiconductor die; and

covering at least a portion of each of the first conductive members with a bond material within the depression located in each of the corresponding conductive material.

2. The method of claim 1 , further comprising heating the bond material to form intermetallics within the depression located in each of the corresponding conductive material.

3. The method of claim 1 , further comprising heating the bond material to fully convert the bond material into one or more intermetallics.

4. The method of claim 1 wherein the bond material includes solder, and wherein the method further includes reflowing the solder.

5. The method of claim 1 , further comprising:

reacting the bond material with a portion of the corresponding first conductive member to form a first intermetallic at least partially within the depression in the corresponding conductive material; and

reacting the bond material with a portion of the corresponding conductive material to form a second intermetallic at least partially within the depression in the corresponding conductive material.

6. The method of claim 5 wherein the first intermetallic and the second intermetallic materials each include tin/nickel (SnNi).

7. The method of claim 5 wherein the first intermetallic includes tin/nickel (SnNi), and the second intermetallic includes tin/copper (SnCu).

8. The method of claim 1 wherein the bond material includes tin/silver (SnAg).

9. The method of claim 1 , further comprising forming a redistribution network on the first semiconductor die, wherein the first semiconductor die includes a plurality of through-substrate interconnects (TSVs) electrically coupled to the redistribution network.

10. The method of claim 1 , further comprising at least partially encasing the first semiconductor die and the second semiconductor die within a thermally conductive casing.

11. The method of claim 1 wherein:

the first conductive members include copper pillars;

the conductive material includes a copper cup;

the first semiconductor die is a logic die or a memory die; and

the second semiconductor die is a logic die or a memory die.

12. The method of claim 1 wherein the conductive material projects toward the first semiconductor die.

13. The method of claim 1 wherein the depression has a curved shape.

14. The method of claim 1 wherein the depression of the corresponding conductive material is defined by a recessed surface of the first conductive member, the method further comprising forming a barrier material over the recessed surface.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050680/0268 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 2 TO PATENT SECURITY AGREEMENT Recorded Feb 10, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041671/0902 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 9, 2016
From: GANDHI, JASPREET S.; HUANG, WAYNE H.; DERDERIAN, JAMES M.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 039385/0956 →
Continuity (2)
Division 14281449 · May 19, 2014
Related Publication 20160343689A1 · Nov 24, 2016