Interconnect structure with improved conductive properties and associated systems and methods
View Patent ↗Interconnect structures with improved conductive properties are disclosed herein. In one embodiment, an interconnect structure can include a first conductive member coupled to a first semiconductor die and a second conductive member coupled to second semiconductor die. The first conductive member includes a recessed surface defining a depression. The second conductive member extends at least partially into the depression of the first conductive member. A bond material within the depression can at least partially encapsulate the second conductive member and thereby bond the second conductive member to the first conductive member.
1. A semiconductor die assembly, comprising:
a first semiconductor die including a substrate, a dielectric material, and a conductive trace between the substrate and the dielectric material, wherein the dielectric material includes an opening, and wherein a portion of the conductive trace is exposed through the opening;
a second semiconductor die; and
a plurality of interconnect structures between the first and second semiconductor dies, wherein at least one of the interconnect structures includes:
a first conductive member projecting from the conductive trace and beyond the dielectric material, wherein the first conductive member includes a recessed surface defining a depression,
a second conductive member coupled to the second semiconductor die, wherein at least a portion of the second conductive member extends into the depression of the first conductive member, and
a bond material within the depression and contacting at least a portion of the second conductive member within the depression, wherein the bond material includes at least one of tin/silver (SnAg), a tin/nickel (SnNi) intermetallic, and a tin/copper (Sn/Cu) intermetallic.
2. The semiconductor die assembly of claim 1 wherein:
the first semiconductor die is a logic die or a memory die; and
the second semiconductor die is a logic die or a memory die.
3. The semiconductor die assembly of claim 1 , further comprising a thermally conductive casing at least partially enclosing the first semiconductor die and the second semiconductor die within an enclosure.
4. The semiconductor die assembly of claim 1 wherein the first conductive member projects toward the second semiconductor die.
5. A semiconductor die assembly, comprising:
a first semiconductor die including a substrate, a dielectric material, and a conductive trace between the substrate and the dielectric material, wherein the dielectric material includes an opening, and wherein a portion of the conductive trace is exposed through the opening;
a second semiconductor die; and
a plurality of interconnect structures between the first and second semiconductor dies, wherein at least one of the interconnect structures includes:
a first conductive member projecting from the conductive trace and beyond the dielectric material, wherein the first conductive member includes a recessed surface defining a depression,
a second conductive member coupled to the second semiconductor die, wherein at least a portion of the second conductive member extends into the depression of the first conductive member, and
a bond material within the depression and contacting at least a portion of the second conductive member within the depression,
wherein a portion of the plurality of interconnect structures includes dummy structures that are not electrically coupled to the first and second semiconductor dies.
6. The semiconductor die assembly of claim 5 wherein:
the first conductive member includes a copper cup; and
the second conductive member includes a copper pillar.
7. The semiconductor die assembly of claim 6 wherein the bond material includes tin/silver solder (SnAg).
8. The semiconductor die assembly of claim 5 wherein the bond material includes:
a first intermetallic at least partially within the depression; and
a second intermetallic in contact with the first intermetallic at least partially within the depression.
9. The semiconductor die assembly of claim 8 wherein the first intermetallic and the second intermetallic each include tin/nickel (SnNi).
10. The semiconductor die assembly of claim 8 wherein the first intermetallic includes tin/nickel (SnNi) the second intermetallic includes tin/copper (SnCu).
11. The semiconductor die assembly of claim 5 wherein the depression has a curved shape.
12. A semiconductor die assembly comprising:
a first semiconductor die including a substrate, a dielectric material, and a conductive trace between the substrate and the dielectric material, wherein the dielectric material includes an opening, and wherein a portion of the conductive trace is exposed through the opening;
a second semiconductor die;
a plurality of interconnect structures between the first and second semiconductor dies, wherein at least one of the interconnect structures includes:
a first conductive member projecting from the conductive trace and beyond the dielectric material, wherein the first conductive member includes a recessed surface defining a depression,
a second conductive member coupled to the second semiconductor die, wherein at least a portion of the second conductive member extends into the depression of the first conductive member, and
a bond material within the depression and contacting at least a portion of the second conductive member within the depression; and
a redistribution network on the first semiconductor die, wherein
the first semiconductor die includes a plurality of through-substrate interconnects (TSVs) electrically coupled to the redistribution network,
a first portion of the plurality of interconnect structures is electrically coupled to individual TSVs of the plurality of TSVs via the redistribution network, and
a second portion of the plurality of interconnect structures is electrically isolated from the redistribution network.
13. A semiconductor die assembly, comprising:
a first semiconductor die including a substrate, a dielectric material, and a conductive trace between the substrate and the dielectric material, wherein the dielectric material includes an opening, and wherein a portion of the conductive trace is exposed through the opening;
a second semiconductor die;
a plurality of interconnect structures between the first and second semiconductor dies, wherein at least one of the interconnect structures includes:
a first conductive member projecting from the conductive trace and beyond the dielectric material, wherein the first conductive member includes a recessed surface defining a depression,
a second conductive member coupled to the second semiconductor die, wherein at least a portion of the second conductive member extends into the depression of the first conductive member, and
a bond material within the depression and contacting at least a portion of the second conductive member within the depression,
wherein
the at least one of the interconnect structures further includes a barrier material over the recessed surface,
the bond material includes a first intermetallic portion reacted with the barrier material and a second intermetallic portion reacted with a material of the second conductive member and
the first intermetallic portion contacts the second intermetallic portion.
14. The semiconductor die assembly of claim 13 wherein:
the barrier material is a first barrier material; and
the at least one of the interconnect structures further includes a second barrier material over a portion of the second conductive member within the depression.
15. The semiconductor die assembly of claim 13 wherein:
the dielectric material includes an edge portion adjacent the opening; and
the first conductive member includes a peripheral portion that extends over the edge portion of the dielectric material.
16. The semiconductor die assembly of claim 15 wherein the peripheral portion has a width between about 5 μm to about 20 μm.
17. The semiconductor die assembly of claim 16 wherein the depression is adjacent the peripheral portion, and wherein the depression has a curved shape.