Multiple data channel memory module architecture
According to one example of the present disclosure, a system includes a computing element configured to provide requests for memory access operations and a memory module comprising a plurality of memories, a plurality of independent data channels, each of the independent data channels coupled to one of the plurality of memories, a plurality of internal address/control channels, each of the independent address/control channels coupled to one of the plurality of memories, and control logic coupled to the plurality of internal address/control channels and configured to receive and decode address and control information for a memory access operation, the control logic further configured to selectively provide the decoded address and control information to a selected internal address/control channel for a selected independent data channel of the plurality of independent data channels based on the received address and control information for the memory access operation.
1. A system comprising:
a computing element configured to provide requests for memory access operations; and
a memory module comprising:
a plurality of memories;
a plurality of independent data channels;
a plurality of independent internal address/control channels; and
control logic coupled to the plurality of independent internal address/control channels and configured to receive and decode address and control information for a memory access operation, the control logic further configured to selectively provide the decoded address and control information to a selected internal address/control channel for a selected independent data channel of the plurality of independent data channels based on the received address and control information for the memory access operation.
2. The system of claim 1 , further comprising:
a memory controller coupled to the computing element and the memory module, the memory controller configured to provide the address and control information responsive to the request for memory access operation.
3. The system of claim 1 , wherein the plurality of independent data channels comprise eight data channels.
4. The system of claim 1 , wherein each memory of the plurality of memories supports sub-cache data access operations.
5. The system of claim 1 , wherein each internal address/control channel is configured to provide decoded address and control information for two internal data channels of the plurality of internal data channels.
6. The system of claim 1 , wherein the plurality of memories comprise dynamic random access memories.
7. The system of claim 1 , wherein the compute element is one of a plurality of heterogenous compute elements.
8. A system comprising:
a plurality of compute elements configured to provide a memory access request;
a memory controller coupled to the compute elements and configured receive the memory access request and to provide address/control information responsive to the memory access request; and
a memory hub comprising:
a plurality of memories coupled to the memory controller by multiple independent data channels; and
control logic coupled to the memory controller by an external address/control channel and to the plurality of memories by a plurality of internal address/control channels, the control logic configured to receive and decode the address/control information and to provide the decoded internal address information to one or more of the plurality of memories to control data transfer over the multiple independent data channels.
9. The system of claim 8 , wherein the memory access request comprises independent memory access requests for the plurality of memories.
10. The system of claim 9 , wherein the control logic is configured to decode the address/control information into component address/control information, wherein each component address/control information corresponds to one of the independent memory access requests.
11. The system of claim 10 , wherein the control logic is configured to decode the address control information based on a time multiplexed encoding scheme.
12. The system of claim 11 , wherein each internal address/control channel of the plurality of internal address/control channels is configured to control data transfer over two of the multiple independent data channels.
13. The system of claim 12 , wherein the control logic is configured to provide a first component address/control information to a first memory over an internal command/address channel during a first time unit and to provide a second component address/control information to a second memory over the internal command address channel during a second time unit.
14. The system of claim 13 , wherein a first independent data channel of the multiple independent data channels is configured to transfer data associated with a first independent memory access request during the first time period and a second independent data channel of the multiple independent data channels is configured to transfer data associated with a second independent memory access request during the second time period.
15. The system of claim 9 , wherein each of the multiple independent data channels is configured to transmit a sub-cache-block of data for the independent memory access requests.
16. The system of claim 8 , wherein the plurality of compute elements comprises heterogeneous compute elements.
17. The system of claim 8 , wherein the plurality compute elements comprises homogeneous compute elements.
18. The system of claim 8 , wherein the multiple independent data channels comprise eight independent data channels.
19. The system of claim 8 , wherein the plurality of internal address/control channels comprises four internal address/control channels.
20. The system of claim 8 , wherein each of multiple independent data channels is configured to perform eight byte data access operations responsive to the decoded address and control information.