IP Library Granted Patent US 9,837,396
Granted Patent B2
US 9,837,396 · App. 15/254,586 · Granted Dec 5, 2017

Stacked semiconductor die assemblies with high efficiency thermal paths and associated methods

Inventors: Sameer S. Vadhavkar (Boise, ID); Xiao Li (Boise, ID); Steven K. Groothuis (Boise, ID); Jian Li (Boise, ID); Jaspreet S. Gandhi (Boise, ID); James M. Derderian (Boise, ID); David R. Hembree (Boise, ID)
Assignee: Micron Technology, Inc.
H01L25/50H01L21/4882H01L21/50H01L21/563H01L23/04H01L23/36H01L23/3675H01L25/0657H01L25/16H01L25/167H01L2224/16145H01L2225/06568H01L2225/06589
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Quick Facts
Patent No.
US 9,837,396
App. No.
15/254,586
Granted
Dec 5, 2017
Kind
B2
Abstract

A semiconductor die assembly having high efficiency thermal paths. In one embodiment, the semiconductor die assembly comprises a package support substrate, a first semiconductor die having a peripheral region and a stacking region, and a second semiconductor die attached to the stacking region of the first die such that the peripheral region is lateral of the second die. The assembly further includes a thermal transfer unit having a base attached to the peripheral region of the first die, a cover attached to the base by an adhesive, and a cavity defined by at least cover, wherein the second die is within the cavity. The assembly also includes an underfill in the cavity, wherein a fillet portion of the underfill extends a distance up along a portion of the footing and upward along at least a portion of the base.

Claims (24)

1. A semiconductor die assembly, comprising:

a package support substrate;

a first semiconductor die having a peripheral region and a stacking site;

a plurality of second semiconductor dies arranged in a stack and mounted to the stacking site of the first die;

a metal casing having first portion and a second portion, the first portion being attached to peripheral region of the first die and having an inner surface, the inner surface being spaced apart from the stack of second dies and extending upward, and the second portion enclosing the stack of second dies, wherein the first portion of the casing comprises an inner casing having a first support attached to the peripheral region of the first die and a cap attached to an uppermost second die of the plurality of second dies, and wherein the second portion comprises an outer casing having a top over the cap of the inner casing and a sidewall attached to the package support substrate; and

an underfill material between the stack of second dies and the first portion of the casing, wherein a portion of the underfill material engages the inner surface of the first portion.

2. The semiconductor die assembly of claim 1 wherein the inner casing further comprises a second support opposite the first support, and the second support is attached to the peripheral region of the first die.

3. A method of manufacturing a semiconductor assembly having a package support substrate, a first semiconductor die mounted to the package support substrate, a plurality of second dies arranged in a stack and mounted to the first die, and a thermal transfer unit having a cavity in which the stack of second dies is positioned, the method comprising:

instilling a thermally conductive dielectric material into the cavity of the thermal transfer unit such that the thermally conductive dielectric material contacts the thermal transfer unit and at least one of the second dies, wherein instilling the thermally conductive dielectric material into the cavity comprises flowing the thermally conductive dielectric material into the cavity in a liquid state; and

sealing the thermal transfer unit to enclose the first die and the second dies within the cavity.

4. The method of claim 3 wherein the thermally conductive dielectric material comprises a paraffin.

5. The method of claim 3 wherein the thermally conductive dielectric material has a thermal conductivity of approximately 0.1 to 0.15 W/mK at 200° C.

6. The method of claim 3 wherein the thermally conductive dielectric material has a thermal conductivity of approximately 0.50 W/mK at 120° C. in a solution of ethylene glycol at 30% by volume.

7. The method of claim 3 wherein the method further comprises at least partially solidifying the liquid state thermally conductive dielectric material in situ in the cavity.

8. The method of claim 3 wherein the method further comprises fully solidifying the liquid state thermally conductive dielectric material in situ in the cavity.

9. The method of claim 3 wherein:

the thermal transfer unit comprises a first portion having a sidewall extending from the package support substrate to at least approximately an uppermost second die of the stack of second dies and a top;

instilling the thermally conductive dielectric material comprises flowing the thermally conductive dielectric material into the cavity while the top is detached from the sidewall; and

the method further comprises attaching the top to the sidewall after flowing the thermally conductive dielectric material into the cavity.

10. The method of claim 3 , further comprises depositing an underfill material at least between the second dies before instilling the thermally conductive dielectric material into the cavity.

11. A method of manufacturing a semiconductor assembly having a package support substrate, a first semiconductor die mounted to the package support substrate, a plurality of second dies arranged in a stack and mounted to the first die, and a thermal transfer unit having a cavity in which the stack of second dies is positioned, the method comprising:

instilling a thermally conductive dielectric material into the cavity of the thermal transfer unit such that the thermally conductive dielectric material contacts the thermal transfer unit and at least one of the second dies, wherein the thermal transfer unit comprises a metal casing having a sidewall attached to at least the package support substrate, a top integrally formed with the sidewall, an inlet, and an outlet; and wherein instilling the thermally conductive dielectric material comprises injecting the thermally conductive dielectric material through the inlet and into the cavity; and

sealing the thermal transfer unit to enclose the first die and the second dies within the cavity.

12. The method of claim 11 , further comprising filling the cavity with the thermally conductive dielectric material at least until the thermally conductive dielectric material passes through the outlet.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050680/0268 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 2 TO PATENT SECURITY AGREEMENT Recorded Feb 10, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041671/0902 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 15, 2016
From: VADHAVKAR, SAMEER S.; LI, XIAO; GROOTHUIS, STEVEN K.; LI, JIAN; GANDHI, JASPREET S.; DERDERIAN, JAMES M.; HEMBREE, DAVID R.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 039759/0101 →
Continuity (2)
Division 14330934 · Jul 14, 2014
Related Publication 20160372452A1 · Dec 22, 2016