Connections for memory electrode lines
Subject matter disclosed herein may relate to word line electrodes and/or digit line electrodes in a cross-point array memory device. One or more word line electrodes may be configured to form a socket area to provide connection points to drivers and/or other circuitry that may be located within a footprint of an array of memory cells.
1. A memory array having a plurality of memory sub-arrays separated by a bare line region and a socket region, the memory array comprising:
a first bundle of conductive lines extending straight and parallel to one another in a first direction and passing through the bare line region;
a second bundle of conductive lines extending parallel to the first direction and passing through the socket region adjacent to the bare line region, each of the second bundle of conductive lines having a horizontal jog in the socket region;
a third bundle of conductive lines extending parallel to the first direction into the socket region and terminating in the socket region, wherein at least two of the third bundle of conductive lines co-terminate at substantially the same position along the first direction and at least one of the third bundle of conductive lines does not co-terminate with the at least two conductive lines and extends farther along the first direction into the socket region; and
wherein the first bundle of conductive lines are separated from the second bundle of conductive lines and the third bundle of conductive lines by a seam extending in the first direction and having a seam space width.
2. The memory array of claim 1 , further comprising a space width between immediately adjacent conductive lines of the third bundle, wherein the seam space width is substantially the same in physical dimension as the space width.
3. The memory array of claim 1 , further comprising a space width between immediately adjacent conductive lines of the third bundle, wherein the seam space width does not exceed twice the space width in physical dimension.
4. The memory array of claim 1 , wherein the at least one conductive line of the third bundle of conductive lines that does not co-terminate deviates substantially from parallel to the first direction before terminating.
5. A method of forming a socket region for making vertical connections to a metal level in an integrated circuit comprising:
forming a plurality of electrically conductive vertical connectors within the socket region;
forming, using a pitch multiplication method, a first bundle of lines that passes through the socket region uninterrupted, the first bundle of lines positioned vertically above the conductive vertical connectors and extending along a first horizontal direction,
each of the first bundle of lines having a jog segment deviating from parallel to the first horizontal direction, wherein at least one of the jog segments intersects a horizontal position of one of the conductive vertical connectors;
forming, using the pitch multiplication method, a second bundle of lines within the socket region simultaneously with the first bundle of lines, the second bundle of lines positioned at the same vertical level as the first bundle of lines and extending along the first horizontal direction; and
forming using a noncritical mask at least two of the second bundle of lines that co-terminate at substantially the same position along the first horizontal direction, and simultaneously forming using the noncritical mask at least one of the second bundle of lines that does not co-terminate and extends farther into the socket region before terminating at a substantially different position along the first horizontal direction.
6. The method of claim 5 , wherein the noncritical mask is a chop mask comprising an opening within a mask layer.
7. The method of claim 5 , wherein the noncritical mask has a printed length in the first horizontal direction exceeding ten times a minimum feature size F, wherein F is a minimum feature size of a memory array.
8. The method of claim 5 , wherein the noncritical mask has a printed width in a direction orthogonal to the first horizontal direction exceeding four times the minimum feature size F, wherein F is a minimum feature size of a memory array.
9. The method of claim 5 , wherein the at least one of the second bundle of lines that does not co-terminate comprises at least two outer lines that include inward jogs before termination.
10. The method of claim 9 , wherein the at least one of the second bundle of lines that does not co-terminate further comprises at least two outer lines that do not include inward jogs and extend farther into the socket region before termination.
11. The method of claim 5 , wherein the noncritical mask has a misalignment tolerance in the direction orthogonal to the first direction of at least twice the minimum feature size F, wherein F is a minimum feature size of a memory array.
12. The method of claim 5 , wherein the shortest distance from an edge of a jog segment to the corresponding edge of an adjacent jog segment in the first direction is at least four times a minimum feature size F, wherein F is a minimum feature size of a memory array.
13. The method of claim 5 , wherein the first bundle of lines and the second bundle of lines comprise electrode lines.
14. The method of claim 5 , wherein the first bundle of lines and the second bundle of lines comprise hard mask lines.
15. The method of claim 5 , wherein the first bundle of lines and the second bundle of lines comprise trenches in a dielectric layer in a damascene process, and wherein the noncritical mask is a blocking mask.
16. A method of forming a memory array, comprising:
forming a first bundle of conductive lines extending in a first direction and passing through a bare line region;
forming a second bundle of conductive lines extending in the first direction and passing through a socket region, each of the second bundle of conductive lines having a jog in the socket region; and
forming a third bundle of conductive lines extending in the first direction and terminating in the socket region;
wherein the first bundle of conductive lines are separated from the second bundle of conductive lines and the third bundle of conductive lines by a seam extending in the first direction and having a seam space width.
17. The method of claim 16 , further comprising forming a space width between immediately adjacent conductive lines of the third bundle of conductive lines, wherein the seam space width is the same as the space width.
18. The method of claim 16 , further comprising forming a space width between immediately adjacent conductive lines of the third bundle, wherein the seam space width is equal to or less than twice the space width.
19. The method of claim 16 , wherein at least two of the third bundle of conductive lines terminate at a first position along the first direction and at least one of the third bundle of conductive lines terminates at a second position along the first direction.
20. The method of claim 19 , wherein the at least one of the third bundle of conductive lines deviates from the first direction before terminating.