Select device for memory cell applications
View Patent ↗The present disclosure includes select devices and methods of using select device for memory cell applications. An example select device includes a first electrode having a particular geometry, a semiconductor material formed on the first electrode and a second electrode having the particular geometry with formed on the semiconductor material, wherein the select device is configured to snap between resistive states in response to signals that are applied to the select device.
1. A method of forming a memory cell of an array of memory cells, the method comprising:
forming a select device, wherein the select device includes:
a first electrode having a particular geometry;
a semiconductor material;
a second electrode having the particular geometry; and
an insulator material formed on sidewalls of the first electrode, the semiconductor material, and the second electrode; and
forming a storage element in series with the select device and the voltage buffer.
2. The method of claim 1 , wherein forming the select device is a back end of line (BEOL) process.
3. The method of claim 1 , wherein a width of the particular geometry is based on an operating voltage associated with the memory cell.
4. The method of claim 1 , wherein a composition of the semiconductor material is based on an operating voltage associated with the memory cell.
5. The method of claim 1 , wherein the method includes forming the select device at a temperature of not greater than approximately 450° C.
6. The method of claim 1 , wherein forming the select device includes the first electrode having a circular geometry.
7. The method of claim 1 , wherein forming the select device includes the first electrode having a quasi-square geometry.
8. A method of forming a memory cell of an array of memory cells, the method comprising:
forming a select device, wherein the select device includes:
a first electrode, wherein the first electrode includes a first laminate portion;
a second electrode, wherein the first electrode includes a second laminate portion;
a semiconductor material between the first and second electrodes; and
an insulator material on sidewalls of the first electrode, the semiconductor material, and the second electrode; and
forming a storage element in series with the select device.
9. The method of claim 8 , wherein the method includes forming a vacuum between the select device and an adjacent select device of the array.
10. The method of claim 8 , wherein the method includes doping the first and second electrodes with an optical absorber.
11. The method of claim 8 , wherein the first laminate portion includes a metal, a resistive material, or another semiconductor material.
12. A method of forming a memory cell of an array of memory cells, the method comprising:
forming a select device of the memory cell, wherein the select device includes:
a first electrode;
a second electrode;
a semiconductor material between the first and second electrodes; and
an insulator material on sidewalls of the first electrode, the semiconductor material, and the second electrode,
wherein the select device is formed such that:
the select device snaps from a first resistive state to a second resistive state in response to providing a first signal to the select device, wherein the first signal is greater than a threshold voltage; and
the select device remains in the first resistive state in response to providing a second signal to the select device, wherein the second signal is less than the threshold voltage; and
forming a storage element in series with the select device.
13. The method of claim 12 , wherein the method includes forming the select device such that:
a first current density is provided to the storage element in response to the select device snapping from the first resistive state to the second resistive state; and
a second current density is provided to the storage element in response to the select device remaining in the first resistive state.
14. The method of claim 13 , wherein the first current density is greater than 1 MA/cm 2 and the second current density is less than or equal to 1 MA/cm 2 .
15. The method of claim 14 , wherein the method includes forming the select device such that the select device snaps from the second resistive state to the first resistive state in response to removing the first signal.
16. The method of claim 12 , wherein the method includes forming the select device such that the select device reaches a temperature greater than 600° C. in response to providing the first signal to the select device.
17. The method of claim 12 , wherein the method includes forming the select device such that:
the select device snaps from the first resistive state to the second resistive state in response to reaching a threshold temperature greater than 600° C.; and
the select device repeatedly reaches the threshold temperature.
18. The method of claim 12 , wherein the method includes:
forming a sense line coupled to the memory cell such that a half select voltage (V/2) can be applied to the sense line; and
forming a access line coupled to the memory cell such that a negative half select voltage (−V/2) can be applied to the access line.
19. The method of claim 12 , wherein the threshold voltage is 2.5 V.