Variable page size architecture
Methods, systems, and devices for operating a memory array with variable page sizes are described. The page size may be dynamically changed, and multiple rows of the memory array may be accessed in parallel to create the desired page size. A memory bank of the array may contain multiple memory sections, and each memory section may have its own set of sense components (e.g., sense amplifiers) to read or program the memory cells. Multiple memory sections may thus be accessed in parallel to create a memory page from multiple rows of memory cells. The addressing scheme may be modified based on the page size. The logic row address may identify the memory sections to be accessed in parallel. The memory sections may also be linked and accessing a row in one section may automatically access a row in a second memory section.
1. A method, comprising:
selecting an active page size that is an integer multiple of a base page size, wherein the base page size is associated with a first number of memory cells within a row of a memory bank for which a memory array is accessible, the first number corresponding to a number of sense components associated with the memory array, and wherein the second number of memory cells within the row are configured to be activated in response to an access command, the second number greater than the first number and greater than the number of sense components associated with the memory array;
configuring an address scheme for the memory bank based at least in part on the active page size; and
sending the access command using the address scheme and according to the active page size.
2. The method of claim 1 , wherein configuring the address scheme comprises:
configuring a logic row address to identify a memory section of a plurality of memory sections of the memory array, a physical row within the memory section, and a physical column section of the physical row.
3. The method of claim 2 , wherein the physical column section comprises a plurality of memory cells equal to the base page size.
4. The method of claim 2 , wherein the physical column section comprises a plurality of physical columns equally spaced along the physical row.
5. The method of claim 1 , wherein configuring the address scheme comprises:
configuring a column address to identify a section of the active page size, wherein the active page size comprises a plurality of sections.
6. The method of claim 5 , wherein the section of the active page size comprises a read burst length.
7. The method of claim 1 , wherein configuring the address scheme comprises:
determining a number of bits for a logic row address based at least in part on the active page size; and
determining a number of bits for a column address based at least in part on the active page size.
8. The method of claim 7 , wherein a sum of the number of bits for the logic row address and the number of bits for the column address is a constant value independent of the active page size.
9. The method of claim 8 , wherein the constant value is based at least in part on a size of the memory bank or a read burst length, or both.
10. The method of claim 1 , further comprising:
determining a linking relationship between a first memory section of a plurality of memory sections and a second memory section of the plurality of memory sections.
11. The method of claim 10 , wherein the first memory section is linked to the second memory section, the active page size is twice the base page size, and the method comprises:
sending a logic row address to a row decoder to open a memory page, wherein the logic row address identifies the first memory section;
opening a first base memory page of the first memory section based at least in part on the logic row address; and
opening a second base memory page of the second memory section based at least in part on a linking between the first memory section and the second memory section, wherein the memory page comprises the first base memory page and the second base memory page.
12. The method of claim 11 , wherein the second base memory page has a same relative address within the second memory section as the first base memory page within the first memory section.
13. The method of claim 10 , wherein the linking relationship is stored in a register.
14. The method of claim 10 , wherein the linking relationship is configurable.
15. The method of claim 1 , wherein selecting the active page size comprises:
selecting the active page size upon powering on a device, wherein the memory array comprises an element of the device.
16. The method of claim 1 , wherein selecting the active page size comprises:
receiving an indication to use a specific page size; and
setting the active page size equal to the specific page size.
17. The method of claim 16 , further comprising:
receiving the indication to use the specific page size from a software application.
18. The method of claim 1 , further comprising:
programming a first plurality of memory cells of the memory bank using the active page size; and
reading a second plurality of memory cells of the memory bank using another active page size that is a different integer multiple or submultiple of the base page size.
19. The method of claim 1 , wherein the base page size is a page size for each memory section of a plurality of memory sections of the memory array.
20. A method, comprising:
identifying a page size from a plurality of page sizes in which a memory array is accessible, the page size being an integer multiple of a base page size, wherein the base page size is associated with a subset of memory cells within a row of the memory array, wherein the subset of memory cells comprises a number of memory cells corresponding to a plurality of sense components associated with the memory array;
accessing the row of the memory array based at least in part on the identified page size, wherein the accessing includes activating each memory cell within the row;
sensing the subset of memory cells of the row via a subset of a plurality of access lines; and
determining a logic value of each memory cell of the subset of memory cells.
21. The method of claim 20 , wherein identifying the page size comprises:
identifying a page size that includes two or more rows of the memory array.
22. The method of claim 20 , wherein selecting the subset of memory cells of the row via the subset of access lines comprises:
activating a first plurality of switches to electronically couple each access line of the subset of access lines to a sense component of the plurality of sense components.
23. The method of claim 22 , wherein a remainder of the plurality of access lines are electrically isolated from the plurality of sense components via a second plurality of switches.
24. The method of claim 22 , further comprising:
receiving a logic row address that identifies the subset of memory cells; and
activating the first plurality of switches based at least in part on the logic row address.
25. The method of claim 20 , wherein accessing the row of the memory array comprises:
activating a plurality of selection components, wherein each memory cell of the row is in electronic communication with a selection component of the plurality of selection components.
26. An apparatus, comprising:
a plurality of row access lines, each row access line of the plurality in electronic communication with a row of memory cells;
a plurality of column access lines, each column access line of the plurality in electronic communication with a column of memory cells;
a plurality of sense components, wherein a number of sense components is less than a number of column access lines; and
a memory controller configurable to select a memory page size that is an integer multiple of a smallest page size, wherein the smallest page size is associated with a first number of memory cells within a row and is based at least in part on the number of sense components corresponding to the first number of memory cells, and wherein a second number of memory cells within the row are configured to be activated in response to an access command, the second number greater than the first number.
27. The apparatus of claim 26 , wherein each sense component of the plurality of sense components is in electronic communication with at least two column access lines, the apparatus further comprising:
a plurality of switches, each switch of the plurality of switches electrically separating a column access line of the plurality of column access lines from a sense component of the plurality of sense components.
28. The apparatus of claim 26 , further comprising:
a row buffer comprising a plurality of latches, wherein each latch of the plurality of latches is in electronic communication with a sense component of the plurality of sense components.
29. The apparatus of claim 26 , wherein the plurality of row access lines and the plurality of column access lines comprise a memory section, the apparatus further comprising:
a plurality of memory sections that comprise a memory bank, wherein each memory section of the plurality of memory sections is associated with a set of sense components.
30. The apparatus of claim 26 , further comprising:
a command generator configurable to issue a logic row address based at least in part on the memory page size.
31. A method, comprising:
accessing a first memory bank of a plurality of memory banks using a first memory page size, wherein the first memory page size is an integer multiple of a base page size associated with a first number of memory cells within a row of the first memory bank, and wherein accessing the first memory bank comprises activating a second number of memory cells within the row, the second number greater than the first number; and
accessing a second memory bank of the plurality of memory banks using a second memory page size that is different from the first memory page size, wherein the second memory page size is a different integer multiple of the base page size, and wherein accessing the second memory bank comprises activating a third number of memory cells within a row of the second memory bank, the third number greater than the first number.
32. The method of claim 31 , further comprising:
accessing the first memory bank using a first addressing scheme that is based at least in part on the first memory page size; and
accessing the second memory bank using a second addressing scheme that is based at least in part on the second memory page size.