IP Library Granted Patent US 9,755,145
Granted Patent B2
US 9,755,145 · App. 15/279,158 · Granted Sep 5, 2017

Memory arrays having confined phase change material structures laterally surrounded with silicon nitride

Inventors: Andrea Redaelli (Casatenovo, IT); Giorgio Servalli (Fara Gera D'Adda, IT); Carmela Cupeta (Milan, IT); Fabio Pellizzer (Boise, ID)
Assignee: Micron Technology, Inc.
H01L45/1293H01L27/2463H01L45/06H01L45/065H01L45/126H01L45/1233H01L45/1286H01L45/141H01L45/144H01L45/1608H01L45/1666H01L45/1675
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Quick Facts
Patent No.
US 9,755,145
App. No.
15/279,158
Granted
Sep 5, 2017
Kind
B2
Abstract

Some embodiments include methods of forming memory cells. Heater structures are formed over an array of electrical nodes, and phase change material is formed across the heater structures. The phase change material is patterned into a plurality of confined structures, with the confined structures being in one-to-one correspondence with the heater structures and being spaced from one another by one or more insulative materials that entirely laterally surround each of the confined structures. Some embodiments include memory arrays having heater structures over an array of electrical nodes. Confined phase change material structures are over the heater structures and in one-to-one correspondence with the heater structures. The confined phase change material structures are spaced from one another by one or more insulative materials that entirely laterally surround each of the confined phase change material structures.

Claims (16)

1. The memory array, comprising:

heater structures over an array of electrical nodes; the heater structures being in one-to-one correspondence with the electrical nodes; the array having rows extending along a first direction and having columns extending along a second direction substantially orthogonal to the first direction; wordlines being under the electrical nodes and extending along the first direction;

confined phase change material structures over the heater structures and in one-to-one correspondence with the heater structures;

bitlines across the confined phase change material structures, with the bitlines extending along the second direction;

conductive material caps between and contacting the bitlines and the confined phase change material structures;

the confined phase change material structures having lateral peripheries of phase change material; and

wherein:

the array has x-direction axes extending through the confined phase change material structures along the first direction and has y-direction axes extending through the confined phase change material structures along the second direction;

the confined phase change material structures and conductive material caps are spaced from one another along the x-direction axes by first insulative material regions comprising a first oxide-containing material having a first pair of opposing vertical sidewalls sandwiched between first nitride-containing materials that extend vertically along an entirety of the first pair of opposing vertical sidewalls;

the confined phase change material structures and conductive material caps are spaced from on another along the y-direction axes by second insulative material regions comprising a second oxide-containing material having a second pair of opposing vertically extending sidewalls sandwiched between second nitride-containing materials that extend vertically along an entirety of the second pair of opposing vertically extending sidewalls;

the first and second nitride-containing materials are silicon nitride; and

the lateral peripheries of the confined phase change material structures, the conductive material caps and the heater structures are entirely laterally surrounded by the first and second nitride-containing materials.

2. The memory array of claim 1 wherein the heater structures are configured as angled plates.

3. The memory array of claim 1 wherein the heater structures are configured as solid rods.

4. The memory array of claim 1 wherein the heater structures are configured as hollow tubes.

5. The memory array of claim 1 wherein the second insulative material regions are about a same depth as the first insulative material regions.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050680/0268 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 2 TO PATENT SECURITY AGREEMENT Recorded Feb 10, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041671/0902 →
Continuity (3)
Division 14799467 · Jul 14, 2015
Division 13948980 · Jul 23, 2013
Related Publication 20170018708A1 · Jan 19, 2017