IP Library Granted Patent US 9,484,536
Granted Patent B2
US 9,484,536 · App. 14/799,467 · Granted Nov 1, 2016

Memory cells, memory arrays, and methods of forming memory cells and arrays

Inventors: Andrea Redaelli (Casatenovo, IT); Giorgio Servalli (Fara Gera d'Adda, IT); Carmela Cupeta (Milan, IT); Fabio Pellizzer (Boise, ID)
Assignee: Micron Technology, Inc.
H01L45/1666H01L27/2463H01L45/06H01L45/126H01L45/1233H01L45/1286H01L45/141H01L45/144H01L45/1608H01L45/1675
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Quick Facts
Patent No.
US 9,484,536
App. No.
14/799,467
Granted
Nov 1, 2016
Kind
B2
Abstract

Some embodiments include methods of forming memory cells. Heater structures are formed over an array of electrical nodes, and phase change material is formed across the heater structures. The phase change material is patterned into a plurality of confined structures, with the confined structures being in one-to-one correspondence with the heater structures and being spaced from one another by one or more insulative materials that entirely laterally surround each of the confined structures. Some embodiments include memory arrays having heater structures over an array of electrical nodes. Confined phase change material structures are over the heater structures and in one-to-one correspondence with the heater structures. The confined phase change material structures are spaced from one another by one or more insulative materials that entirely laterally surround each of the confined phase change material structures.

Claims (24)

1. A method of forming memory cells, comprising:

forming a plurality of heater structures over an array of electrical nodes; the array of electrical nodes having rows extending along a first direction and having columns extending along a second direction substantially orthogonal to the first direction; wordlines being under the array of electrical nodes and extending along the first direction;

forming a phase change material across the plurality of heater structures;

patterning the phase change material into a plurality of confined structures; the plurality of confined structures being spaced from one another by one or more insulative materials that entirely laterally surround each of the confined structures in the plurality of confined structures; each confined structure of the plurality of confined structures being associated with only a single memory cell; and

forming bitlines across the plurality of confined structures, with the bitlines extending along the second direction; and

wherein the plurality of heater structures are patterned from heater material strips that extend along the first direction and along paired rows of the array of electrical nodes; and wherein the patterning of the phase change material into the plurality of confined structures comprises:

forming first trenches through the phase change material and the heater material strips, with the first trenches extending along the first direction and cutting the heater material strips into lines of heater material that are in one-to-one correspondence with the rows of the array of electrical nodes;

lining the first trenches with a first insulative material of the one or more insulative materials;

after forming and lining the first trenches, forming second trenches through the phase change material and the lines of heater material, with the second trenches extending along the second direction and patterning the lines of heater material into the plurality of heater structures; and

lining the second trenches with a second insulative material of the one or more insulative materials.

2. The method of claim 1 wherein the first and second insulative materials are non-oxygen-containing materials.

3. The method of claim 1 wherein the heater material strips are configured as upwardly opening containers, and wherein the plurality of heater structures are configured as angled plates.

4. A method of forming memory cells, comprising:

forming lines of a first insulative material over an array of electrical nodes; the array of electrical nodes having rows extending along a first direction and having columns extending along a second direction substantially orthogonal to the first direction; wordlines being under the array of electrical nodes and extending along the first direction; the lines of the first insulative material extending along the first direction and being along paired rows of the array of electrical nodes; the lines of the first insulative material forming an undulating topography across the array of electrical nodes;

forming an expanse of heater material across the undulating topography;

planarizing the expanse of heater material to remove heater material from over the lines of the first insulative material and thereby pattern the heater material into strips; the strips extending along the first direction and across paired rows of the array of electrical nodes; the strips of heater material being configured as upwardly-opening containers;

forming a chalcogenide across the strips;

forming first trenches through the chalcogenide and the strips of heater material, with the first trenches extending along the first direction and cutting the strips into lines of heater material that are in one-to-one correspondence with the rows of the array of electrical nodes;

lining the first trenches with a second insulative material;

after forming and lining the first trenches, forming second trenches through the chalcogenide and the lines of heater material, with the second trenches extending along the second direction and patterning the heater material into heater structures while patterning the chalcogenide into confined structures;

lining the second trenches with a third insulative material; and

forming bitlines across the confined structures, with the bitlines extending along the second direction.

5. The method of claim 4 wherein the first, second and third insulative materials have a common composition.

6. The method of claim 4 wherein the first, second and third insulative materials all comprise silicon nitride.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
Continuity (2)
Division 13948980 · Jul 23, 2013
Related Publication 20150325627A1 · Nov 12, 2015