IP Library Granted Patent US 9,112,150
Granted Patent B2
US 9,112,150 · App. 13/948,980 · Granted Aug 18, 2015

Methods of forming memory cells and arrays

Inventors: Andrea Redaelli (Casatenovo, IT); Giorgio Servalli (Fara Gera D'Adda, IT); Carmela Cupeta (Milan, IT); Fabio Pellizzer (Cornate D'Adda, IT)
Assignee: Micron Technology, Inc.
H01L45/1666H01L27/2463H01L45/141H01L45/1608
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Quick Facts
Patent No.
US 9,112,150
App. No.
13/948,980
Granted
Aug 18, 2015
Kind
B2
Abstract

Some embodiments include methods of forming memory cells. Heater structures are formed over an array of electrical nodes, and phase change material is formed across the heater structures. The phase change material is patterned into a plurality of confined structures, with the confined structures being in one-to-one correspondence with the heater structures and being spaced from one another by one or more insulative materials that entirely laterally surround each of the confined structures. Some embodiments include memory arrays having heater structures over an array of electrical nodes. Confined phase change material structures are over the heater structures and in one-to-one correspondence with the heater structures. The confined phase change material structures are spaced from one another by one or more insulative materials that entirely laterally surround each of the confined phase change material structures.

Claims (24)

1. A method of forming memory cells, comprising:

forming a plurality of heater structures over an array of electrical nodes; the array of electrical nodes having rows extending along a first direction and having columns extending along a second direction substantially orthogonal to the first direction; wordlines being under the array of electrical nodes and extending along the first direction;

forming a phase change material across the plurality of heater structures;

patterning the phase change material into a plurality of confined structures; the plurality of confined structures being spaced from one another by one or more insulative materials that entirely laterally surround each of the confined structures in the plurality of confined structures;

forming bitlines across the plurality of confined structures, with the bitlines extending along the second direction; and

wherein the plurality of heater structures are patterned from lines of heater material that extend along the first direction, and wherein the patterning of the phase change material into the plurality of confined structures comprises:

forming first trenches through the phase change material, with the first trenches extending along the first direction;

lining the first trenches with a first insulative material of the one or more insulative materials;

after forming and lining the first trenches, forming second trenches through the phase change material and the lines of heater material, with the second trenches extending along the second direction and patterning the lines of heater material into the plurality of heater structures; and

lining the second trenches with a second insulative material of the one or more insulative materials.

2. The method of claim 1 wherein the first and second insulative materials are non-oxygen-containing materials.

3. The method of claim 2 wherein the first and second non-oxygen-containing insulative materials have a same composition as one another.

4. The method of claim 2 wherein the first and second non-oxygen-containing insulative materials have different compositions relative to one another.

5. A method of forming memory cells, comprising:

forming lines of heater material over an array of electrical nodes; the array of electrical nodes having rows extending along a first direction and having columns extending along a second direction substantially orthogonal to the first direction; wordlines being under the array of electrical nodes and extending along the first direction; the lines of heater material extending along the first direction and being along rows of the array of electrical nodes;

forming a chalcogenide over the lines of heater material and across the array of electrical nodes;

forming first trenches through the chalcogenide, with the first trenches extending along the first direction;

lining the first trenches with a first insulative material;

after forming and lining the first trenches, forming a patterned bitline material over the chalcogenide; the patterned bitline material forming bitline material lines extending along the second direction;

using the patterned bitline material as a mask during formation of second trenches through the chalcogenide and the lines of heater material, with the second trenches extending along the second direction and patterning the lines of heater material into heater structures while patterning the chalcogenide into confined structures; and

lining the second trenches with a second insulative material.

6. The method of claim 5 wherein the first and second insulative materials comprise silicon nitride.

7. The method of claim 5 wherein a cap of an electrically conductive material is formed over the chalcogenide, and is patterned into blocks over the chalcogenide as the chalcogenide is patterned into the confined structures.

8. The method of claim 7 wherein the cap of the electrically conductive material comprises one or more of Ti, TiN, W, C, Ta and TaN; where the chemical formulas indicate primary components rather than specific stoichiometries.

Assignments (9)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE ADDRESS PREVIOUSLY RECORDED ON REEL 030860 FRAME 0902. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jul 25, 2013
From: REDAELLI, ANDREA; SERVALLI, GIORGIO; CUPETA, CARMELA; PELLIZZER, FABIO
To: MICRON TECHNOLOGY, INC.
Reel/Frame 030889/0253 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 23, 2013
From: REDAELLI, ANDREA; SERVALLI, GIRGIO; CUPETA, CARMELA; PELLIZZER, FABIO
To: MICRON TECHNOLOGY, INC.
Reel/Frame 030860/0902 →
Continuity (1)
Related Publication 20150028283A1 · Jan 29, 2015