IP Library Granted Patent US 10,573,513
Granted Patent B2
US 10,573,513 · App. 15/244,629 · Granted Feb 25, 2020

Semiconductor structures including liners comprising alucone and related methods

Inventors: Zhe Song (Boise, ID); Tuman E. Allen (Kuna, ID); Cole S. Franklin (Boise, ID); F. Daniel Gealy (Kuna, ID)
Assignee: Micron Technology, Inc.
H01L21/02178H01L21/0228H01L21/02118H01L21/02362H01L21/0337H01L27/11582H01L27/2409H01L27/2427H01L45/06H01L45/065H01L45/126H01L45/1233H01L45/141H01L45/1608H01L45/1675
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,573,513
App. No.
15/244,629
Granted
Feb 25, 2020
Kind
B2
Abstract

A semiconductor device including stacked structures. The stacked structures include at least two chalcogenide materials or alternating dielectric materials and conductive materials. A liner including alucone is formed on sidewalls of the stacked structures. Methods of forming the semiconductor device are also disclosed.

Claims (19)

1. A semiconductor device, comprising:

stack structures comprising a first chalcogenide material over a material and a second chalcogenide material over the first chalcogenide material; and

a liner over sidewalls of at least a portion of the stack structures, the liner comprising a first portion comprising aluminum oxide in contact with the sidewalls of the stack structures and a second portion comprising alucone over the first portion, the second portion further comprising silicon atoms, nitrogen atoms, or a combination thereof.

2. The semiconductor device of claim 1 , wherein the liner comprises a gradient of alucone and aluminum oxide over the sidewalls of the stack structures.

3. The semiconductor device of claim 1 , wherein the liner comprises a ratio of aluminum oxide to alucone of from about 1:1 to about 1:10.

4. The semiconductor device of claim 1 , wherein the liner overlies an entirety of the sidewalls.

5. The semiconductor device of claim 1 , wherein the liner further comprises a third portion between the first portion and the second portion, the third portion comprising a greater amount of alucone than the first portion.

6. The semiconductor device of claim 1 , wherein adjacent stack structures of the stack structures are separated from each other by a distance of between about 20 nm and about 60 nm.

7. A semiconductor device, comprising:

stack structures comprising at least one chalcogenide material over a material; and

a liner comprising a first portion comprising aluminum oxide contacting opposing sidewalls of the stack structures and a second portion comprising alucone over the first portion.

8. The semiconductor device of claim 7 , wherein the liner has a thickness of between about 5 Å and about 30 Å.

9. The semiconductor device of claim 7 , further comprising a charge trapping material over the liner.

10. The semiconductor device of claim 7 , wherein the liner comprises a gradient of alucone, a concentration of alucone increasing from about zero percent at a portion of the liner proximal the stack structures to about one-hundred percent at a portion of the liner distal from the stack structures.

11. A method of forming a semiconductor device, the method comprising:

forming stack structures over a material, forming the stack structures comprising forming a first chalcogenide material over the material and forming a second chalcogenide material over the first chalcogenide material;

forming aluminum oxide over and in contact with sidewalls of the stack structures; and

forming alucone over the aluminum oxide.

12. The method of claim 11 , wherein forming alucone over the aluminum oxide comprises forming the alucone to exhibit a gradient of alucone and aluminum oxide.

Assignments (4)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050680/0268 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 2 TO PATENT SECURITY AGREEMENT Recorded Feb 10, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041671/0902 →
Continuity (2)
Continuation 14189323 · Feb 25, 2014
Related Publication 20160365514A1 · Dec 15, 2016