IP Library Granted Patent US 10,573,379
Granted Patent B2
US 10,573,379 · App. 15/266,271 · Granted Feb 25, 2020

Determining soft data

Inventors: Violante Moschiano (Avezzano, IT); Andrea D'Alessandro (L'Aquila, IT); Andrea Giovanni Xotta (Castelgomberto, IT)
Assignee: Micron Technology, Inc.
G11C11/5642G06F11/1012G06F11/1068G11C29/52H03M13/45G11C2029/0411
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Quick Facts
Patent No.
US 10,573,379
App. No.
15/266,271
Granted
Feb 25, 2020
Kind
B2
Abstract

The present disclosure includes apparatuses and methods for determining soft data. A number of embodiments include determining soft data associated with a data state of a memory cell. In a number of embodiments, the soft data may be determined by performing a single stepped sense operation on the memory cell.

Claims (46)

1. An apparatus, comprising:

an array of NAND flash memory cells;

sense circuitry, wherein the sense circuitry includes:

a capacitance coupled to a memory cell of the array;

an analog-to-digital (ADC) converter coupled to a first plate of the capacitance; and

a boost driver coupled to a second plate of the capacitance; and

a controller configured to operate the sense circuitry to:

sense a single value associated with the memory cell by applying a single stepped sensing signal to the memory cell, wherein the sensed single value is a current on a data line to which the memory cell is coupled that is directly correlated to a threshold voltage of the memory cell; and

determine soft data associated with a data state of the memory cell based on the sensed single value by:

determining, based on the sensed single value, a voltage associated with the capacitance coupled to the memory cell while the single stepped sensing signal is being applied to the memory cell; and

determining the soft data based on the determined voltage using the ADC converter coupled to the first plate of the capacitance and the boost driver coupled to the second plate of the capacitance.

2. The apparatus of claim 1 , wherein the soft data associated with the data state of the memory cell includes at least two soft data values.

3. The apparatus of claim 1 , wherein the controller is configured to operate the sense circuitry to determine the data state of the memory cell based on the sensed single value.

4. The apparatus of claim 1 , wherein the controller includes an error correction component configured to correct an error associated with the data state of the memory cell using the determined soft data.

5. The apparatus of claim 1 , wherein the soft data associated with the data state of the memory cell indicates:

a location of the threshold voltage of the memory cell within a threshold voltage distribution associated with the data state of the memory cell; and

a probability of whether the threshold voltage of the memory cell corresponds to the data state of the memory cell.

6. The apparatus of claim 1 , wherein the memory cell is a multilevel memory cell.

7. A method for operating memory, comprising:

sensing a single value associated with a NAND flash memory cell by applying a single stepped sensing signal to the memory cell, wherein the sensed single value is a current on a data line to which the memory cell is coupled that is directly correlated to a threshold voltage of the memory cell; and

determining soft data associated with a data state of the memory cell based on the sensed single value, wherein the soft data is determined by:

determining, based on the sensed single value, a voltage associated with a capacitance coupled to the memory cell while the single stepped sensing signal is being applied to the memory cell; and

determining the soft data based on the determined voltage using an analog-to-digital (ADC) converter coupled to a first plate of the capacitance and a boost driver coupled to a second plate of the capacitance; and

wherein the determined soft data includes at least two soft data values.

8. The method of claim 7 , wherein the single stepped sensing signal steps down from a number of different voltage levels.

9. The method of claim 7 , wherein the single stepped sensing signal steps up from a number of different voltage levels.

10. An apparatus, comprising:

an array of NAND flash memory cells;

sense circuitry, wherein the sense circuitry includes:

a capacitance coupled to a memory cell of the array;

an analog-to-digital (ADC) converter coupled to a first plate of the capacitance; and;

a boost driver coupled to a second plate of the capacitance; and

a controller configured to operate the sense circuitry to:

sense a single value associated with the memory cell by applying a single stepped sensing signal to the memory cell, wherein the sensed single value is a current on a data line to which the memory cell is coupled that is directly correlated to a threshold voltage of the memory cell;

determine a data state of the memory cell based on the sensed single value; and

determine soft data associated with the data state of the memory cell based on the sensed single value by:

determining, based on the sensed single value, a voltage associated with the capacitance coupled to the memory cell while the single stepped sensing signal is being applied to the memory cell; and

determining the soft data based on the determined voltage using the ADC converter coupled to the first plate of the capacitance and the boost driver coupled to the second plate of the capacitance.

11. The apparatus of claim 10 , wherein the ADC converter and the boost driver are configured to convert the determined voltage to a digital value corresponding to the soft data.

12. The apparatus of claim 10 , wherein the voltage associated with the capacitance coupled to the memory cell is determined based on a supply voltage associated with applying the single stepped sensing signal to the memory cell.

13. The apparatus of claim 10 , wherein the voltage associated with the capacitance coupled to the memory cell is determined based on a duration for which the single stepped sensing signal is applied to the memory cell.

14. The apparatus of claim 10 , wherein:

the capacitance is coupled to the data line; and

the ADC converter is coupled to the data line.

15. The apparatus of claim 14 , wherein:

the second plate of the capacitance is opposite the first plate of the capacitance.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050680/0268 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
SUPPLEMENT NO. 2 TO PATENT SECURITY AGREEMENT Recorded Feb 10, 2017
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041671/0902 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 15, 2016
From: MOSCHIANO, VIOLANTE; D'ALESSANDRO, ANDREA; XOTTA, ANDREA GIOVANNI
To: MICRON TECHNOLOGY, INC.
Reel/Frame 039756/0339 →