Sense circuits, semiconductor devices, and related methods for resistance variable memory
View Patent ↗Sense circuits, memory devices, and related methods are disclosed. A sense circuit includes sample and hold circuitry configured to sample and hold a second response voltage potential, a first response voltage potential, and a third response voltage potential responsive to an evaluation signal applied to a resistance variable memory cell. The sense circuit includes an amplifier operably coupled to the sample and hold circuitry. The amplifier is configured to amplify a difference between a sum of the first response voltage potential and the third response voltage potential, and twice the second response voltage potential. A memory device includes an evaluation signal generating circuit configured to provide the evaluation signal, an array of resistance variable memory cells, and the sense circuit. A method includes applying the evaluation signal to the resistance variable memory cell, sampling and holding the response voltage potentials, and discharging the sample and hold circuitry to the amplifier.
1. A sense circuit, comprising:
sample and hold circuitry operably coupled to a data sense line and configured to sample and hold a first response voltage potential, a second response voltage potential, and a third response voltage potential responsive to respective values of an evaluation signal comprising three different values being applied to a resistance variable memory cell operable in multiple data states, a third value being greater than a second value and the second value being greater than a first value;
circuitry operably coupled to the sample and hold circuitry and configured to determine a data state of the resistance variable memory cell by comparing a difference between the first and second response voltage potentials to a difference between the second and third response potentials.
2. The sense circuit of claim 1 , wherein the evaluation signal comprises a current and a second current value is about equally spaced between respective values of a first current value and a third current value.
3. The sense circuit of claim 1 , wherein the circuitry configured to determine a data state of the resistance variable memory cell comprises:
a switched capacitor amplifier operably coupled to the sample and hold circuitry and configured to amplify a difference between a sum of the first response voltage potential and the third response voltage potential, and twice the second response voltage potential; and
a latch circuit operably coupled to the switched capacitor amplifier and configured to differentially sense and store a voltage change of an output of the switched capacitor amplifier.
4. The sense circuit of claim 3 , wherein the sample and hold circuitry includes a reference capacitor operably coupled to a non-inverting input of an operational amplifier of the switched capacitor amplifier, the reference capacitor configured to sample a buffered version of the second response voltage potential, and hold the non-inverting input to the buffered version of the second response voltage potential.
5. The sense circuit of claim 4 , wherein the sample and hold circuitry includes a capacitor operably coupled to an inverting input of an operational amplifier of the switched capacitor amplifier, and configured to sample and hold a buffered version of the first response voltage potential; and
another capacitor operably coupled to the inverting input and configured to sample and hold a buffered version of the third response voltage potential.
6. The sense circuit of claim 5 , wherein the other capacitor has a capacitance value larger than a capacitance value of the capacitor.
7. The sense circuit of claim 5 , wherein the other capacitor has a capacitance value that is about the same as a capacitance value of the capacitor.
8. The sense circuit of claim 5 , wherein the switched capacitor amplifier includes a feedback capacitor and a feedback switch operably coupled in parallel with each other from the inverting input to an output of the switched capacitor amplifier.
9. The sense circuit of claim 8 , wherein the capacitor has a capacitance value that is greater than a capacitance value of the feedback capacitor.
10. The sense circuit of claim 8 , wherein the capacitor has a capacitance value that is at least about fifteen (15) times as large as a capacitance value of the feedback capacitor.
11. The sense circuit of claim 3 , wherein the switched capacitor amplifier is further configured to amplify a difference between the third response voltage potential and the second response voltage potential.
12. The sense circuit of claim 1 , further comprising a buffer configured to buffer the data sense line from at least a portion of the sample and hold circuitry.
13. The sense circuit of claim 12 , wherein the buffer includes a source follower circuit.
14. A semiconductor device, comprising:
an evaluation signal generating circuit for providing an evaluation signal including three values;
an array of resistance variable memory cells, each resistance variable memory cell of the array configured to switch from a first data state to a second data state responsive to a greatest value of the three values; and
sense circuitry configured to operably couple to a selected resistance variable memory cell of the array and determine a data state of the selected resistance variable memory cell by:
sampling and holding a first response voltage potential responsive to a first value of the evaluation signal, a second response voltage potential responsive to a second value of the evaluation signal, and a third response voltage potential responsive to a third value of the evaluation signal; and
comparing a difference between the first and second response voltage potentials to a difference between the second and third response voltage potentials.
15. The semiconductor device of claim 14 , wherein each resistance variable memory cell of the array comprises a spin torque transfer (STT) memory cell.
16. A method, comprising:
applying a signal to a resistance variable memory cell;
sampling and holding first, second and third voltage potentials responsive to the signal;
amplifying a difference between a sum of the first and third voltage potentials and twice the second voltage potential;
analyzing the amplified difference to determine a data state of the resistance variable memory cell; and
applying another signal to switch the resistance variable memory cell to a data state corresponding to a preselected, determined data state.
17. The method of claim 16 , wherein sampling and holding the voltage potentials comprises sampling and holding buffered versions of one or more of the voltage potentials.
18. The method of claim 16 , wherein amplifying the difference between a sum of the first and third voltage potentials and twice the second voltage potential comprises amplifying the difference with one of a switch capacitor amplifier and a switch capacitor inverting amplifier.
19. The method of claim 16 , wherein analyzing the amplified difference comprises applying the amplified difference to latch circuitry.
20. The method of claim 16 , wherein applying another signal to switch the resistance variable memory cell to a data state corresponding to a preselected, determined data state comprises applying the other signal to switch the resistance variable memory cell back to a data state existing prior to the application of the signal.