Programming methods and memories

1. A method of programming a memory, comprising:

boosting a channel voltage while a first portion of a plurality of increasing programming pulses is applied to a selected access line; and

when a criteria is met, reducing the channel voltage to a reduced voltage level and subsequently boosting the channel voltage, starting from the reduced voltage level, while a second portion of the plurality of increasing programming pulses is applied to the selected access line;

wherein differences between the channel voltage, when the channel voltage is boosted while the first portion of the plurality of increasing programming pulses is applied to the selected access line, and voltages of the first portion of the plurality of increasing programming pulses are substantially the same as differences between the channel voltage, when the channel voltage is boosted while the second portion of the plurality of increasing programming pulses is applied to the selected access line, and voltages of the second portion of the plurality of increasing programming pulses.

2. The method of claim 1 , further comprising:

applying a plurality of increasing first inhibit voltage pulses to an unselected access line while the first portion of the plurality of increasing programming pulses is applied to the selected access line;

when the criteria is met, reducing a voltage of a final first inhibit voltage pulse of the plurality of increasing first inhibit voltage pulses and that occurs when a final programming pulse of the first portion of the plurality of increasing programming pulses occurs to a voltage of an initial second inhibit voltage pulse of a plurality increasing second inhibit voltage pulses and that occurs when an initial programming pulse of the second portion of the plurality of increasing programming pulses occurs; and

applying the plurality of increasing second inhibit voltage pulses to the unselected access line while the second portion of the plurality of increasing programming pulses is applied to the selected access line.

3. The method of claim 1 , further comprising:

applying a plurality of increasing first inhibit voltage pulses to an unselected access line while the first portion of the plurality of increasing programming pulses is applied to the selected access line;

when the criteria is met, increasing a voltage of a final first inhibit voltage pulse of the plurality of increasing first inhibit voltage pulses and that occurs when a final programming pulse of the first portion of the plurality of increasing programming pulses occurs to a voltage of an initial second inhibit voltage pulse of a plurality increasing second inhibit voltage pulses and that occurs when an initial programming pulse of the second portion of the plurality of increasing programming pulses occurs; and

applying the plurality of increasing second inhibit voltage pulses to the unselected access line while the second portion of the plurality of increasing programming pulses is applied to the selected access line.

4. The method of claim 1 , wherein the first portion of the plurality of programming pulses is applied in a region of the memory having a pattern in which data lines immediately adjacent to and on each side of an inhibited data line are not inhibited is dominant in the memory.

5. The method of claim 1 , wherein the second portion of the plurality of programming pulses is applied in a region of the memory where a majority of cells being inhibited are connected to data lines having immediately adjacent data lines on each side thereof inhibited.

6. The method of claim 1 , wherein the criteria is selected from the group consisting of a determined number of programming pulses, a determined average threshold voltage of memory cells being programmed, completion of a determined level of programming, and dominance of a CS0 pattern over a CS2 pattern.

7. The method of claim 1 , wherein programming the memory comprises programming a single page of the memory, wherein the criteria is a certain point in the programming of the single page of the memory.

8. The method of claim 1 ,

wherein the channel voltage comprises a plurality of increasing first voltages that occur while the first portion of the plurality of increasing programming pulses is applied to the selected access line, wherein a final first voltage of the plurality of increasing first voltages occurs when a final programming pulse of the first portion of the plurality of increasing programming pulses occurs;

wherein the channel voltage comprises a plurality of increasing second voltages, starting from an initial second voltage of the plurality of increasing second voltages that is at the reduced voltage level, that occur while the second portion of the plurality of increasing programming pulses is applied to the selected access line, wherein the initial second voltage of the plurality of increasing second voltages occurs when an initial programming pulse of the second portion of the plurality of increasing programming pulses occurs;

wherein the differences between the channel voltage, when the channel voltage is boosted while the first portion of the plurality of increasing programming pulses is applied to the selected access line, and the voltages of the first portion of the plurality of increasing programming pulses comprises a difference between the final first voltage of the plurality of increasing first voltages and a voltage of the final programming pulse of the first portion of the plurality of increasing programming pulses;

wherein the differences between the channel voltage, when the channel voltage is boosted while the second portion of the plurality of increasing programming pulses is applied to the selected access line, and the voltages of the second portion of the plurality of increasing programming pulses comprises a difference between the initial second voltage of the plurality of increasing second voltages and a voltage of the initial programming pulse of the second portion of the plurality of increasing programming pulses; and

wherein the difference between the final first voltage of the plurality of increasing first voltages and the voltage of the final programming pulse of the first portion of the plurality of increasing programming pulses is substantially the same as the difference between the initial second voltage of the plurality of increasing second voltages and the voltage of the initial programming pulse of the second portion of the plurality of increasing programming pulses.

9. The method of claim 8 , further comprising, shifting a voltage applied to an unselected access line from a voltage level of the voltage applied to the unselected access line that occurs when the final programming pulse of the first portion of the plurality of programming pulses is applied to a lower voltage level of the voltage applied to the unselected access line that occurs when the initial programming pulse of the second portion of the plurality of programming pulses is applied.

10. The method of claim 1 , wherein boosting the channel voltage comprises applying a voltage to an unselected access line, and further comprising grounding an access line on either side of the unselected access line while applying the voltage to the unselected access line.

11. A memory device, comprising:

control circuitry;

wherein the control circuitry is configured to boost a channel voltage while a first portion of a plurality of increasing programming pulses is applied to a selected access line;

wherein the control circuitry is configured, when a criteria is met, to reduce the channel voltage to a reduced voltage level and to subsequently boost the channel voltage, starting from the reduced voltage level, while a second portion of the plurality of increasing programming pulses is applied to the selected access line; and

wherein differences between the channel voltage, when the channel voltage is boosted while the first portion of the plurality of increasing programming pulses is applied to the selected access line, and voltages of the first portion of the plurality of increasing programming pulses are substantially the same as differences between the channel voltage, when the channel voltage is boosted while the second portion of the plurality of increasing programming pulses is applied to the selected access line, and voltages of the second portion of the plurality of increasing programming pulses.

12. The memory device of claim 11 ,

wherein the control circuitry is configured to apply a plurality of increasing first inhibit voltage pulses to an unselected access line while the first portion of the plurality of increasing programming pulses is applied to the selected access line;

wherein the control circuitry is configured, when the criteria is met, to reduce a voltage of a final first inhibit voltage pulse of the plurality of increasing first inhibit voltage pulses and that occurs when a final programming pulse of the first portion of the plurality of increasing programming pulses occurs to a voltage of an initial second inhibit voltage pulse of a plurality increasing second inhibit voltage pulses and that occurs when an initial programming pulse of the second portion of the plurality of increasing programming pulses occurs; and

wherein the control circuitry is configured to apply the plurality of increasing second inhibit voltage pulses to the unselected access line while the second portion of the plurality of increasing programming pulses is applied to the selected access line.

13. The memory device of claim 11 ,

wherein the control circuitry is configured to apply a plurality of increasing first inhibit voltage pulses to an unselected access line while the first portion of the plurality of increasing programming pulses is applied to the selected access line;

wherein the control circuitry is configured, when the criteria is met, to increase a voltage of a final first inhibit voltage pulse of the plurality of increasing first inhibit voltage pulses and that occurs when a final programming pulse of the first portion of the plurality of increasing programming pulses occurs to a voltage of an initial second inhibit voltage pulse of a plurality increasing second inhibit voltage pulses and that occurs when an initial programming pulse of the second portion of the plurality of increasing programming pulses occurs; and

wherein the control circuitry is configured to apply the plurality of increasing second inhibit voltage pulses to the unselected access line while the second portion of the plurality of increasing programming pulses is applied to the selected access line.

14. The memory device of claim 11 , wherein the control circuitry being configured to boost the channel voltage comprises the control circuitry being configured to apply a voltage to an unselected access line, wherein the control circuitry is configured to ground an access line on either side of the unselected access line while the voltage is applied to the unselected access line.

15. The memory device of claim 11 , wherein the criteria is selected from the group consisting of a determined number of programming pulses, a determined average threshold voltage of memory cells being programmed, completion of a determined level of programming, and dominance of a CS0 pattern over a CS2 pattern.

16. The memory device of claim 11 , wherein the criteria is a certain point during programming of a single page of the memory device.

17. A memory device, comprising:

control circuitry;

wherein the control circuitry is configured to boost a channel voltage while a first portion of a plurality of increasing programming pulses is applied to a selected access line, wherein the channel voltage comprises a plurality of increasing first voltages that occur while the first portion of the plurality of increasing programming pulses is applied to the selected access line, wherein a final first voltage of the plurality of increasing first voltages occurs when a final programming pulse of the first portion of the plurality of increasing programming pulses occurs;

wherein the control circuitry is configured, when a criteria is met, to reduce the channel voltage to a reduced voltage level and to subsequently boost the channel voltage, starting from the reduced voltage level, while a second portion of the plurality of increasing programming pulses is applied to the selected access line, wherein the channel voltage comprises a plurality of increasing second voltages, starting from an initial second voltage of the plurality of increasing second voltages that is at the reduced voltage level, that occur while the second portion of the plurality of increasing programming pulses is applied to the selected access line, wherein the initial second voltage of the plurality of increasing second voltages occurs when an initial programming pulse of the second portion of the plurality of increasing programming pulses occurs;

wherein differences between the channel voltage, when the channel voltage is boosted while the first portion of the plurality of increasing programming pulses is applied to the selected access line, and voltages of the first portion of the plurality of increasing programming pulses are substantially the same as differences between the channel voltage, when the channel voltage is boosted while the second portion of the plurality of increasing programming pulses is applied to the selected access line, and voltages of the second portion of the plurality of increasing programming pulses;

wherein the differences between the channel voltage, when the channel voltage is boosted while the first portion of the plurality of increasing programming pulses is applied to the selected access line, and the voltages of the first portion of the plurality of increasing programming pulses comprises a difference between the final first voltage of the plurality of increasing first voltages and a voltage of the final programming pulse of the first portion of the plurality of increasing programming pulses;

wherein the differences between the channel voltage, when the channel voltage is boosted while the second portion of the plurality of increasing programming pulses is applied to the selected access line, and the voltages of the second portion of the plurality of increasing programming pulses comprises a difference between the initial second voltage of the plurality of increasing second voltages and a voltage of the initial programming pulse of the second portion of the plurality of increasing programming pulses; and

wherein the difference between the final first voltage of the plurality of increasing first voltages and the voltage of the final programming pulse of the first portion of the plurality of increasing programming pulses is substantially the same as the difference between the initial second voltage of the plurality of increasing second voltages and the voltage of the initial programming pulse of the second portion of the plurality of increasing programming pulses.

18. The memory device of claim 17 , wherein the criteria is selected from the group consisting of a determined number of programming pulses, a determined average threshold voltage of memory cells being programmed, completion of a determined level of programming, and dominance of a CS0 pattern over a CS2 pattern.

19. The memory device of claim 17 , wherein the control circuitry is configured to shift a voltage applied to an unselected access line from a voltage level of the voltage applied to the unselected access line that occurs when the final programming pulse of the first portion of the plurality of programming pulses is applied to a lower voltage level of the voltage applied to the unselected access line that occurs when the initial programming pulse of the second portion of the plurality of programming pulses is applied.

20. The memory device of claim 17 , wherein the criteria is a certain point during programming of a single page of the memory device.